Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al. (US 20190096791 A1) in view of Tseng et al. (US 2021/0305112 A1).
Regarding independent claim 1: Jeng teaches (e.g., Figs. 1A-1F) a semiconductor package comprising:
a lower redistribution structure ([0015]: 102);
a second semiconductor chip ([0020]: 100);
wherein the second semiconductor chip (100) includes a heat dissipation pad ([0028]: TV) that is disposed at an upper surface of the second semiconductor chip (100);
a lower conductive pillar ([0026]: Left side conductive pillar TIV adjacent to chip 100) disposed on a second region of the lower redistribution structure (periphery of redistribution structure 102),
a heat dissipation pillar ([0030]: TB1 considered a bump due to its shape protruding from the lower surface) disposed on the heat dissipation pad (TV);
an upper redistribution structure ([0031]: 202).
Jeng does not expressly teach
a first semiconductor chip disposed on a first region of the lower redistribution structure;
wherein, when viewed in a plan view, the second region is disposed outside an outer boundary of the first region;
an upper conductive pillar disposed on the lower conductive pillar;
a heat dissipation structure disposed on the heat dissipation pillar.
Tseng teaches (e.g., Figs. 15 and 18; [0050]) a semiconductor package comprising:
a first semiconductor chip ([0049]-[0050]: semiconductor chip 102 located at the topmost level; “referring to FIG. 14 and FIG. 15”) disposed on a first region of a lower redistribution structure (center portion of a lower redistribution structure, which is the layer above structure 230 and below layer 200);
wherein, when viewed in a plan view, the second region ([0024]: regions dedicated for through via 132) is disposed outside an outer boundary of the first region (Fig. 18, [0024]-[0025] and [0030]; when viewed in a plan view, the second region, which is the peripheral region) is disposed outside an outer boundary of the first region (Fig. 18; center portion of a lower redistribution structure, which is the layer above structure 230 and below layer 200);
an upper conductive pillar ([0050]: 140) disposed on a lower conductive pillar ([0050]: lower conductive pillar 140 [0047]);
a heat dissipation structure ([0027] and [0051]: 118) disposed on a heat dissipation pillar ([0050]: 1162).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date include in the device of Jeng,
the first semiconductor chip disposed on a first region of the lower redistribution structure; wherein, when viewed in a plan view, the second region is disposed outside an outer boundary of the first region; an upper conductive pillar disposed on the lower conductive pillar; a heat dissipation structure disposed on the heat dissipation pillar, as taught by Tseng, for the benefits of more efficiently conducting heat from the devices in operation because using the conductive pillars in stacked configuration provide a heat transfer path towards the heatsink, thus improving device reliability by avoiding electrical melting and thermal damage due to heat concentration in the device during operation.
Allowable Subject Matter
Claims 2-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“a first bonding member covering a side surface of the upper conductive pillar; and a second bonding member covering a side surface of the heat dissipation pillar”.
Regarding claim 3: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein the heat dissipation pillar includes a lower end contacting the heat dissipation pad and an upper end contacting the heat dissipation structure,
wherein heat generated from the second semiconductor chip is dissipated to the outside of the semiconductor package via the heat dissipation pillar and the heat dissipation structure”.
Regarding claim 4: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein the heat dissipation structure contacts the heat dissipation pillar”.
Regarding claim 5: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein the heat dissipation structure includes:
a lower heat dissipation plate contacting the heat dissipation pillar; and an upper heat dissipation plate disposed on the lower heat dissipation plate”.
Regarding claim 6: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein the second semiconductor chip further includes:
a heat dissipation via disposed below the heat dissipation pad; and a passivation layer covering a side surface of the heat dissipation via”.
Regarding claim 7: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein a lower surface of the upper conductive pillar is coplanar with a lower surface of the heat dissipation pillar”.
Regarding claim 8: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein the upper redistribution structure has an opening in which the heat dissipation structure is disposed, and wherein the upper redistribution structure surrounds the heat dissipation structure”.
Regarding claim 9: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein the heat dissipation structure is electrically separated from the upper redistribution structure”.
Regarding claim 10: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein a height of the upper conductive pillar is the same as a height of the heat dissipation pillar”.
Claim 11 depends from claim 10 and therefore, is allowable for the same reason as claim 10.
Regarding claim 12: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein a diameter of the upper conductive pillar is greater than a diameter of the lower conductive pillar”.
Regarding claim 13: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein the upper conductive pillar has a diameter having a value selected from a range of about 0.005 mm to about 0.1 mm”.
Regarding claim 14: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein a diameter of the heat dissipation pillar is smaller than the diameter of the upper conductive pillar”.
Regarding claim 15: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
a semiconductor package comprising:
“wherein the heat dissipation structure has a thickness having a value selected from a range of about 0.001 mm to about 0.1 mm”.
Claims 16-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 16: the most relevant prior art references (e.g., Figs. 1A-1F of US 20190096791 A1 to Jeng et al. and Figs. 15 and 18 of US 2021/0305112 A1 to Tseng et al., either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor package comprising:
“wherein the upper redistribution structure has an opening exposing a portion of the second connection layer; and a heat dissipation structure disposed in the opening and connected to the heat dissipation pillar”.
Claims 17-19 depend from claim 16 and therefore, is allowable for the same reason as claim 16.
Regarding claim 20: the most relevant prior art references (e.g., Figs. 1A-1F of US 20190096791 A1 to Jeng et al. and Figs. 15 and 18 of US 2021/0305112 A1 to Tseng et al., either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor package comprising:
“wherein the upper redistribution structure includes an opening in which the heat dissipation structure is disposed, and
wherein the upper redistribution structure surrounds the heat dissipation structure”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812