Prosecution Insights
Last updated: April 19, 2026
Application No. 18/378,789

INTERCONNECT STRUCTURE INCLUDING METAL LINE AND TOP VIA FORMED THROUGH DIFFERENT PROCESSES

Non-Final OA §102§103
Filed
Oct 11, 2023
Examiner
AHMED, SHAHED
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
91%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
866 granted / 955 resolved
+22.7% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
45 currently pending
Career history
1000
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 955 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is responsive to application No. 18378789 filed on 10/11/2023. Information Disclosure Statement Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Election/Restrictions Applicant’s election without traverse of claims 1-16 in the reply filed on 12/11/2025 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2024/0096785). Regarding independent claim 1, Choi et al. teach a semiconductor device comprising: a frontside structure comprising at least one of a front-end-of-line (FEOL) structure (Fig. 1, element 110, paragraph 0030), a middle-of-line (MOL) structure, and a back-end-of-line (BEOL) structure; a 1st metal line (Fig. 1, element 175B, paragraph 0053) on the frontside structure; and a 2nd metal line (Fig. 1, element 175A, paragraph 0053) on the frontside structure, wherein the 1st metal line has a greater width than the 2nd metal line in a same direction (Fig. 1, paragraph 0049), and wherein the 1st metal line and the 2nd metal line have an equal height (Fig. 1). Regarding claim 2, Choi et al. teach further comprising a 1st top via (Fig. 1, element 150H, paragraph 0054) on the 1st metal line without an intervening layer. Regarding claim 3, Choi et al. teach further wherein the 1st top via and the 1st metal line comprise a same material composition (paragraph 0047, 0050 disclose that the vias and metal line comprise of metal). Regarding claim 7, Choi et al. teach further comprising a 2nd top via (Fig. 1, element 150G, paragraph 0054) on the 2nd metal line without an intervening layer therebetween, wherein the 1st top via and the 2nd top via have an equal height (Fig. 1). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2024/0096785). Regarding claim 4, Choi et al. teach wherein the 1st top via and the 1st metal line comprise ruthenium (Ru) (Before the effective filling date of the invention it would have been obvious to one having ordinary skill in the art to select a known metal such as ruthenium as disclosed by Choi in paragraph 0015 , since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416). Claims 5-6, 8-16 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2024/0096785) in view of Hsu et al. (US 2024/0312840). Regarding claim 5, Choi et al. teach all of the limitations as discussed above. Choi et al. do not explicitly disclose wherein a material structure of the 1st top via is different from a material structure of the 1st metal line and the 2ndmetalline. Hsu et al. teach an interconnect structure comprising using different deposition process to form metal lines and vias in the same interconnect level (paragraph 0050) which would result in the metal line and via having different microstructures. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Choi et al. according to the teachings of Hsu et al. with the motivation to improve performance of integrated circuits (ICs) (paragraph 0002). Regarding claim 6, Choi et al. modified by Hsu et al. teach wherein the 1st top via has an amorphous or polycrystalline structure, and the 1st metal line and the 2nd metal line have a columnar material structure (Hsu teaches different process can be used for the via and metal lines (paragraph 0050). Accordingly, it would be obvious to one of ordinary skill in the art that the via can have different material structure such as amorphous/polycrystalline/columnar structure). Regarding Independent claim 8, Choi et al. teach a semiconductor device comprising: a frontside structure comprising at least one of a front-end-of-line (FEOL) structure (Fig. 1, element 110, paragraph 0030), a middle-of-line (MOL) structure, and a back-end-of-line (BEOL) structure; a 1st metal line (Fig. 1, element 175A, paragraph 0054); and a 1st top via (Fig. 1, element 150G, paragraph 0054) on the 1st metal line without an intervening layer therebetween, wherein the 1st metal line and the 1st top via have a same material composition (paragraph 0047, 0050 disclose that the vias and metal line comprise of metal). Choi et al. do not explicitly disclose wherein the 1st metal line and the 1st top via have different material structures. Hsu et al. teach an interconnect structure comprising using different deposition process to form metal lines and vias in the same interconnect level (paragraph 0050) which would result in the metal line and via having different microstructures. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Choi et al. according to the teachings of Hsu et al. with the motivation to improve performance of integrated circuits (ICs) (paragraph 0002). Regarding claim 9, Choi et al. modified by Hsu et al. teach wherein the 1st metal line has a columnar material structure, and the 1st top via has an amorphous or polycrystalline structure (Hsu teaches different process can be used for the via and metal lines (paragraph 0050). Accordingly, it would be obvious to one of ordinary skill in the art that the via can have different material structure such as amorphous/polycrystalline/columnar structure). Regarding claim 10, Choi et al. teach a 2nd metal line (Fig. 1, element 175B, paragraph 0053); and a 2nd top via (Fig. 1, element 150H, paragraph 0054) on the 2ndmetalline, wherein the 2nd metal line has a greater width than the1st metal line in a same direction (Fig. 1), and wherein the 1st metal line and the 2nd metal line have a same height (Fig. 1). Regarding claim 11, Choi et al. teach wherein the 1st top via and the2nd top via have an equal height (Fig. 1). Regarding claim 12, Choi et al. modified by Hsu et al. teach wherein the 2nd metal line and the 2nd top via have different material structures (Hsu et al. teach an interconnect structure comprising using different deposition process to form metal lines and vias in the same interconnect level (paragraph 0050) which would result in the metal line and via having different microstructures). Regarding claim 13, Choi et al. modified by Hsu et al. teach wherein the 1st metal line and the 2nd metal line have a same material structure, and wherein the 1st top via and the 2nd top via have a same material structure (paragraph 0047, 0050 of Choi disclose that the vias and metal line comprise of metal and Hsu et al. teach an interconnect structure comprising using different deposition process to form metal lines and vias in the same interconnect level (paragraph 0050) which would result in the metal line and via having different microstructures). Regarding claim 14, Choi et al. modified by Hsu et al. teach wherein the 1st metal line and the 2nd metal line have a columnar material structure, and the 1st top via and the 2nd top via have an amorphous or polycrystalline structure (Hsu teaches different process can be used for the via and metal lines (paragraph 0050). Accordingly, it would be obvious to one of ordinary skill in the art that the via can have different material structure such as amorphous/polycrystalline/columnar structure). Regarding claim 15, Choi et al. modified by Hsu et al. teach wherein the 1st metal line, the2nd metal line, the 1st top via, and the 2nd top via have a same material composition (paragraph 0047, 0050 of Choi disclose that the vias and metal line comprise of metal). Regarding claim 16, Choi et al. modified by Hsu et al. teach wherein the 1st metal line, the2nd metal line, the 1st top via, and the 2nd top via comprise ruthenium (Ru) (Before the effective filling date of the invention it would have been obvious to one having ordinary skill in the art to select a known metal such as ruthenium as disclosed by Choi in paragraph 0015 , since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAHED AHMED/ Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Oct 11, 2023
Application Filed
Feb 25, 2026
Non-Final Rejection — §102, §103
Mar 27, 2026
Interview Requested
Apr 14, 2026
Applicant Interview (Telephonic)
Apr 14, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604673
JOSEPHSON JUNCTION DEVICE AND METHOD OF MAKING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604589
DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604498
MEMORY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12604502
NANOCHANNEL GALLIUM NITRIDE-BASED DEVICE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Apr 14, 2026
Patent 12598762
METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH LOCAL ISOLATION AND A SEMICONDUCTOR DEVICE WITH LOCAL ISOLATION
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
91%
With Interview (+0.0%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 955 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month