DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Note from the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 and 103 rejections have been provided in parenthesis.
Specification
The disclosure is objected to because of the following informalities:
paragraph [0048] discloses: “may introduce an intended lateral symmetry in the crack stop structure leading to the different mentioned functions of the crack barrier section and the sacrificial section”. However, does the applicant intend to disclose a possible introduction of intended lateral asymmetry? If so, [0048] should be corrected to “may introduce an intended lateral asymmetry in the crack stop structure leading to the different mentioned functions of the crack barrier section and the sacrificial section”.
paragraph [0058] discloses: “[s]uch a trench formed in a surface region of the substrate may interrupt horizontal trench propagation in an efficient way”. This sentence should be corrected to read: “[s]uch a trench formed in a surface region of the substrate may interrupt horizontal crack propagation in an efficient way”.
paragraph [0086] mentions a “crack defeating structure”, but [00102] and [00103] refer to the same structure as a “crack arresting structure”. The name of the disclosed structure should be standardized to avoid confusion.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 10, 15, and 17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Specifically, in claims 10, 15, and 17, it is unclear which features the applicant intends to claim in the respective options recited in the claim language.
Claim 10 recites “The electronic chip according to claim 9, comprising at least one of the following features:”. The phrase “at least one of the following” and the subsequent colon indicates that a list of possible options for claimed subject matter will follow. Applicant then recites four phrases, each separated by a semicolon. However, it is unclear whether the possible features to choose from refer to the subject matter recited in each semicolon-delimited phrase or to the various distinct features mentioned in each phrase. In other words, the meaning of the word “features” is unclear: are there four possible claim limitations to choose from or are there more? Given this ambiguity and for the purpose of continued examination, the examiner will construe the “features” as referring to the four semicolon-delimited phrases recited after the colon and will examine the claim limitation related to the crack-inhibiting function of the crack barrier section: the electronic chip according to claim 9, wherein the crack barrier section is configured as a barrier for inhibiting propagation of a crack through the crack barrier section towards the active region.
Similar ambiguities regarding the meaning of the word “features” exists in claims 15 and 17.
For claim 15, the examiner will construe the “features” as referring to the three semicolon-delimited phrases recited after the colon and will examine the claim limitation requiring that the electronic chip be configured as a bare die: the electronic chip according to claim 1, wherein the electronic chip is configured as bare die.
For claim 17, the examiner will construe the “features” as referring to the four semicolon-delimited phrases recited after the colon and will examine the claim limitation requiring that the crack propagation inhibiting trench be formed in the passivation layer and extend into the BEOL dielectric: the electronic chip according to claim 16, wherein the at least one crack propagation inhibiting trench is formed at least partially in a passivation layer of the substrate, in particular extending into a back end of the line dielectric of the substrate below the passivation layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Claims 1-12, 14, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ning (US 20150162285 A1), hereinafter referred to as “Ning”.
Regarding claim 1. Ning discloses an electronic chip (fig. 3; see [0027]), comprising: a substrate (see fig. 3 and [0027]: “[t]he exemplary semiconductor structure can include a substrate 200 having a device region 201, and a seal ring region 202 surrounding the device region 201. A dielectric layer 203 can be disposed on the surface of the substrate 200”; the entire disclosed structure can be regarded as a substrate, while substrate 200 can specifically be regarded as a semiconductor body) comprising a central portion (fig. 3, 201) and an edge portion (fig. 3 (c.f. fig. 5), 202; see [0054]-[0056] and note that the only difference between the embodiment of fig. 3 and the embodiment of fig. 5 is the inclusion of second seal ring structure 220) around at least part of the central portion (see fig. 3);
an active region arranged in the central portion (see [0033]: active chip circuity is formed within device region 201);
and a crack guiding structure (see annotated fig. 5 above) combined with a crack stop structure (fig. 5, 210; see [0036]-[0038]), both being arranged in the edge portion (see fig. 5).
Regarding claim 2, Ning discloses the electronic chip according to claim 1, wherein the crack guiding structure (see annotated fig. 5 above) defines a spatially confined crack propagation path at least partially inside of the crack stop structure (the crack guiding structure of Ning defines a spatially confined path for the propagation of a crack originating in substrate 200; [0056] confirms that first seal ring structure 210 prevents cracks from entering device region 201; thus, when a crack enters first seal ring structure through the indicated crack guiding structure, the crack cannot propagate through the sub-connection layers 204a and conductive plugs 205; thus, the crack is confined to a path within portions of dielectric layer 203 in between the component structures of first seal ring structure 210: the crack guiding structure defines such a path).
Regarding claim 3, Ning discloses the electronic chip according to claim 1, wherein the crack guiding structure (see annotated fig. 5 above) is configured for redirecting a propagation direction of a crack (see annotated fig. 5 above) when passing the crack guiding structure combined with the crack stop structure (fig. 5, 210; see [0079]: first seal ring structure 210 is configured as a stoppage barrier for preventing crack propagation into device region 201; an exemplary crack (see annotated fig. 5 above) will, thus, be redirected when propagating within the crack guiding structure through first seal ring structure 210).
Regarding claim 4, Ning discloses the electronic chip according to claim 1, wherein the crack guiding structure (see annotated fig. 5 above) is configured for redirecting a crack (see annotated fig. 5 above) propagating towards the active region (fig. 5, 201) into an upwardly propagating crack (see annotated fig. 5 above and [0079]; since first seal ring structure 210 acts as a barrier that prevents cracks from propagating towards the device region 201, an exemplary crack starting in substrate 200 will be redirected upwards upon encountering one of the component structures of 210 such as the crack barrier section along the path defined by the crack guiding structure (as shown above)), wherein in particular the crack guiding structure is configured for further redirecting the upwardly propagating crack into a crack propagating laterally away from the active region (see annotated fig. 5 above and [0079]; since first seal ring structure 210 acts as a barrier that prevents cracks from propagating towards the device region 201, an exemplary crack that has been redirected upwards by one of the plurality of component structures of first seal ring structure 210 is further redirected into a crack propagating laterally away from the device region 201 by another component structure of 210 such as the metallic bulk structure (as shown above)).
Regarding claim 5, Ning discloses the electronic chip according to claim 1, wherein the crack stop structure (fig. 5, 210) is configured for stopping a crack, as a barrier for a crack and/or for absorbing energy of a crack (see [0079]: “[t]he seal ring structure can have vias and metal sub-connection layers in a staggered arrangement, [and] can serve as a stoppage barrier to prevent or slow down crack propagation into the device region”).
Regarding claim 6, Ning discloses the electronic chip according to claim 1, wherein the substrate (see fig. 3 and [0027]: “[t]he exemplary semiconductor structure can include a substrate 200 having a device region 201, and a seal ring region 202 surrounding the device region 201. A dielectric layer 203 can be disposed on the surface of the substrate 200”; the entire disclosed structure can be regarded as a substrate, while substrate 200 can specifically be regarded as a semiconductor body;
also see [0054]-[0056] and note that the only difference between the embodiment of fig. 3 and the embodiment of fig. 5 is the inclusion of second seal ring structure 220) comprises a semiconductor body (fig. 5, 200) with a back end of the line structure (see fig. 5 and [0004]-[0005]; the semiconductor device of Ning includes inter-layer dielectric films (e.g. dielectric layer 203) formed on substrate 200 which further encase the seal ring structures along with active wiring and contact portions; these structures can collectively be regarded as a back end of the line structure atop substrate 200 (and the chip circuit formed therein within device region 201 (see [0033]))) thereon, and wherein the crack guiding structure (see annotated fig. 5 above) combined with the crack stop structure (fig. 5, 210) form part of the back end of the line structure.
Regarding claim 7, Ning discloses the electronic chip according to claim 1, wherein the crack guiding structure (see annotated fig. 5 above) defines a dielectric path (the crack guiding structure defines a path through dielectric layer 203 within first seal ring structure 210) delimited by metallic structures (fig. 5, connection layers 204 and conductive plugs 205; see [0036]: component structures of first seal ring 210 are metallic) of the crack stop structure (fig. 5, 210), wherein in particular the dielectric path comprises a bottom-sided upward path section (see annotated fig. 5 above) merging into a top-sided lateral path section (see annotated fig. 5 above; the crack guiding structure includes (1) a bottom-sided upward path section near the interface between dielectric layer 203 and substrate 200 and (2) a top-sided lateral path section beneath the indicated metallic bulk structure of first seal ring 210) .
Regarding claim 8, Ning discloses the electronic chip according to claim 1, wherein the crack stop structure (fig. 5, 210) comprises horizontal metallic structures (fig. 5, 204a; see [0036]-[0037]) and vertical metallic structures (fig. 5, 205; see [0036] and [0038]).
Regarding claim 9, Ning discloses the electronic chip according to claim 1, wherein a bottom-sided portion of the crack stop structure (see annotated fig. 5 above) comprises a crack barrier section (see annotated fig. 5 above: the crack barrier section is the indicated conductive plug 205; relative to the sacrificial section, the indicated crack barrier section faces the active device region 201) facing the active region and comprises a sacrificial section (see annotated fig. 5 above: the sacrificial section is the indicated portion of seal ring structure 210 laterally adjacent to the indicated crack barrier section and facing away from the active device region 201) facing away from the active region, wherein at least part of the crack guiding structure extends between the crack barrier section and the sacrificial section (see annotated fig. 5 above).
Regarding claim 10 (applicant is reminded of the 112(b) rejection of claim 10 above), Ning discloses the electronic chip according to claim 9, wherein the crack barrier section (see annotated fig. 5 above) is configured as a barrier for inhibiting propagation of a crack through the crack barrier section towards the active region (see [0079]: “The seal ring structure can have vias and metal sub-connection layers in a staggered arrangement, such that the seal ring structure can serve as a stoppage barrier to prevent or slow down crack propagation into the device region, i.e., the functional chip circuit”; note that the indicated crack barrier section in the annotated fig. 5 above comprises a component conductive plug 205 of seal ring structure 210).
Regarding claim 11, Ning discloses the electronic chip according to claim 9, wherein a top-sided portion of the crack stop structure (see annotated fig. 5 above) comprises a metallic bulk structure (see annotated fig. 5 above and [0036]-[0037]; the metallic bulk structure is the indicated sub-connection layer 204a that is coplanar with a top surface of dielectric layer 203; the metallic bulk structure extends vertically from and is connected with the indicated crack barrier section;
see [0030]: “[t]he top of a first conductive plug 205 can be connected to a first connection layer 204”) extending vertically from and being connected with the crack barrier section (see annotated fig. 5 above).
Regarding claim 12, Ning discloses the electronic chip according to claim 11, wherein the metallic bulk structure (see annotated fig. 5 above) is separated by a vertical spacing (see annotated fig. 5 above; the indicated metallic bulk structure lies above the indicated sacrificial section and is separated by a vertical spacing defined by the indicated crack guiding structure) from the sacrificial section and extends laterally over at least part of the sacrificial section (see annotated fig. 5 above; the indicated metallic bulk structure extends over part of the indicated sacrificial section as shown).
Regarding claim 14, Ning discloses the electronic chip according to claim 1, comprising a seal ring (fig. 5, 220; see [0054]) arranged laterally between the active region (fig. 5, 201) on the one hand and the crack guiding structure (see annotated fig. 5 above) combined with the crack stop structure (fig. 5, 210) on the other hand (see fig. 5; second seal ring structure 220 is arranged between device region 201 and first seal ring structure 210).
Regarding claim 19, Ning discloses a manufacturing method (see [0003]), wherein the method comprises:
providing a wafer comprising a plurality of integrally connected electronic chips according to claim 1 (see [0033]; the semiconductor chip disclosed in Ning has a saw lane region and undergoes a chip sawing process whereby the chip is separated from a common wafer;
also see [0054]-[0056] and note that the only difference between the embodiment of fig. 3 and the embodiment of fig. 5 is the inclusion of second seal ring structure 220)
and separating the electronic chips from the wafer along separation lines (see [0033]) extending between adjacent edge portions of the electronic chips (fig. 5, 202; see [0033]; since the semiconductor chip of fig. 3 is cut from a common wafer as disclosed in [0033], the disclosed saw lane region lies between adjacent seal ring regions 202 of individual semiconductor chips) so that at least part of cracks created during the separating are guided along the crack guiding structures (see annotated fig. 5 above) and/or are stopped by the crack stop structures (fig. 5, 210; see [0048]: “first seal ring structure 210 can substantially completely isolate the device region 201 from the saw lane region, to better protect device region 201 and prevent the cracking or delamination generated at the saw lane region during a chip sawing process from extending into the device region 201”).
Regarding claim 20, Ning discloses the method according to claim 19, wherein the method comprises separating the electronic chips from the wafer by mechanical dicing, by laser dicing, or by another chip separation technique (see [0033]; the semiconductor chip of Ning is separated from a common wafer by mechanical dicing (i.e. “chip sawing process”)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claim 13 is rejected under 35 U.S.C. 103 as obvious over Ning in view of West et al. (US 20030122220 A1), hereinafter referred to as “West”.
Ning discloses the electronic chip according to claim 1, wherein the crack stop structure (Ning fig. 5, 210) comprises a plurality of vertically stacked and mutually spaced horizontal metal structures (Ning fig. 5, 204a; see Ning [0036]-[0037]; [0036] discloses that first seal ring structure 210 is composed of metal, so sub-connection layers 204a are metal structures; [0037] discloses (and fig. 5 confirms) that sub-connection layers 204a are arranged vertically (i.e. stacked) in a staggered formation (with overlapping partial vertical alignment); see annotated Ning fig. 5 above and note that the indicated plurality of sub-connection layers 204a are mutually spaced in that there is a regular spacing between the vertically adjacent layers by nature of the layers’ parallel surfaces).
Ning fails to disclose wherein the horizontal metal structures have a thickness which increases from bottom to top of the crack stop structure.
West discloses seal ring structures (see West fig. 1A) for inhibiting the propagation of cracks in integrated circuit (IC) chips caused by wafer dicing (see West [0037]-[0042]) wherein the seal ring structures comprise a plurality of vertically stacked and mutually spaced horizontal metal structures (West fig. 1A, 120; see West [0061] and note that electrically conductive layers 120 are composed of metal; West fig. 1A shows a plurality electrically conductive layers 120 that are vertically stacked and mutually spaced in that there is a regular spacing between any given pair of vertically adjacent layers by nature of the layers’ parallel surfaces) having a thickness which increases from bottom to top of the crack stop structure (see West fig. 1A: the seal ring structure in seal region 104 can be regarded as a crack stop structure; see West [0061] and fig. 1A: “several layers [120] may typically be in the thickness range between about 0.4 and 0.7 .mu.m, while later depositions may have an increased thickness from about 0.8 to 1.2 .mu.m”; note that this increasing thickness from bottom (earlier deposition layers) to top (later deposition layers) is shown in West fig. 1A).
The bottom-to-top increasing thickness teachings of West are incorporated into the crack stop structure of Ning wherein the combination discloses a plurality of vertically stacked and mutually spaced horizontal metal structures having a thickness which increases from bottom to top of the crack stop structure.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the crack stop structure of Ning with the increasing thickness teachings of West to reduce the amount of metallic deposition material used in fabricating the crack stop structure while maintaining robust crack-inhibiting functionality.
Claim 15 is rejected under 35 U.S.C. 103 as obvious over Ning in view of Sinha et al. (US 20200373250 A1), hereinafter referred to as “Sinha”.
Ning discloses the electronic chip according to claim 1.
Ning fails to explicitly disclose wherein the electronic chip is configured as bare die (applicant is reminded of the 112(b) rejection of claim 15 above).
Sinha discloses a back-end-of-line crack stop structure (Sinha fig. 8, 102; see [0065]) in an integrated circuit (IC) chip (see Sinha [0087]) that is configured as bare die (see Sinha [0087]).
The bare die teachings of Sinha are applied to the semiconductor chip of Ning wherein the combination discloses wherein the electronic chip is configured as bare die.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to apply the bare die teachings of Sinha to the semiconductor chip of Ning to reduce costs associated with chip packaging.
Claims 16-17 are rejected under 35 U.S.C. 103 as obvious over Ning in view of Jeng et al. (US 20090115024 A1), hereinafter referred to as “Jeng”.
Regarding claim 16, Ning discloses the electronic chip according to claim 1.
Ning fails to disclose the chip comprising at least one crack propagation inhibiting trench formed in the substrate and being configured for inhibiting horizontal propagation of a crack.
Jeng discloses a semiconductor chip (see Jeng fig. 4A and [0009]) with a seal ring structure (Jeng fig. 4A, seal rings 42 and 44; see Jeng [0025]), wherein the semiconductor chip comprises at least one crack propagation inhibiting trench (Jeng fig. 4A, 66; see Jeng [0034]) formed in the substrate (see Jeng fig. 4A; the substrate includes semiconductor substrate 30 (which can be regarded as a semiconductor body), ILD 34, low-k dielectric layers 50, top dielectric layer 52, first passivation layer Pass-1, and second passivation layer Pass-2) and being configured for inhibiting horizontal propagation of a crack (see Jeng [0035]: “bottom 68 of trench 66 may also be below interface 62, or at other positions as shown in dashed lines. Advantageously, with bottom 68 below interface 62, the cracks propagated along interface 62 may be stopped”; also see Jeng fig. 4A and note that a crack propagating along interface 62 would be substantially horizontal).
The crack propagation inhibiting trench of Jeng is incorporated into the semiconductor chip of Ning.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the trench propagation inhibiting trench teachings of Jeng into the semiconductor chip of Ning to release the stress imparted by certain horizontally propagating cracks (see Jeng [0033]; also see [0034]-[0035] and note that the only substantial difference between the embodiment of fig. 3B and the embodiment of fig. 4A is the location of trench 66).
Regarding claim 17 (applicant is reminded of the 112(b) rejection of claim 17 above), Ning and Jeng disclose the electronic chip according to claim 16, wherein the at least one crack propagation inhibiting trench (Jeng fig. 4A, 66; see Jeng [0034]) is formed at least partially in a passivation layer (Jeng fig. 4A, Pass-2; see Jeng [0027]) of the substrate (see Jeng fig. 4A; the substrate includes semiconductor substrate 30 (which can be regarded as a semiconductor body), ILD 34, low-k dielectric layers 50, top dielectric layer 52, first passivation layer Pass-1, and second passivation layer Pass-2), in particular extending into a back end of the line dielectric (Jeng fig. 4A, 52; see [0026]; also see [0002] and note that invention of Jeng relates to the “back end” stage of semiconductor chip fabrication) of the substrate below the passivation layer (see Jeng fig. 4A and [0034]: “the bottom 68 of trench 66 may extend below the interface 62 [between first passivation layer Pass-1 and top dielectric layer 52]”).
Claim 18 is rejected under 35 U.S.C. 103 as obvious over Ning in view of Hudson (US 20110068435 A1), hereinafter referred to as “Hudson”.
Ning discloses an electronic chip according to claim 1.
Ning fails to disclose a package, comprising: a carrier; said electronic chip mounted on the carrier; and an encapsulant encapsulating at least part of the electronic chip and the carrier.
Hudson discloses a semiconductor chip package (Hudson fig. 1; see Hudson [0024]), comprising:
a carrier (Hudson fig. 1, 20);
an electronic chip (Hudson fig. 1, 15) mounted on the carrier;
and an encapsulant (Hudson fig. 1, 30; see Hudson [0027] and fig. 11: underfill material 30 is composed of epoxy resin and encapsulates part of chip 15 and carrier substrate 20) encapsulating at least part of the electronic chip and the carrier.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the chip package teachings of Hudson with the semiconductor chip taught in Ning to protect the semiconductor chip from further environmental damage such as moisture damage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNER F COLLINS whose telephone number is (571)272-5187. The examiner can normally be reached M-F, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at (571)272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818