DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 and/or 103 rejections are provided in parenthesis.
Response to Amendment
The amendments filed on May 6th, 2026, have been entered. Claims 1-22 are currently pending in this application. Claims 1-2, 4, 10, 15, and 17 have been amended, and new claims 21-22 have been added. Applicant’s amendments to the Specification and Claims overcome all objections and 112(b) rejections previously set forth in the Non-final Office Action mailed February 23rd, 2026.
Claim Objections
Claim 10 is objected to because of the following informalities: “and” should be included before the phrase: “wherein the sacrificial section is configured for being at least partially destroyed by a crack propagating to the crack stop structure”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12, 14-15, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ning (US 20150162285 A1), hereinafter referred to as “Ning”.
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Regarding claim 1. Ning discloses an electronic chip (fig. 3; see [0027]), comprising: a substrate (see fig. 3 and [0027]: “[t]he exemplary semiconductor structure can include a substrate 200 having a device region 201, and a seal ring region 202 surrounding the device region 201. A dielectric layer 203 can be disposed on the surface of the substrate 200”; the entire disclosed structure can be regarded as a substrate, while substrate 200 can specifically be regarded as a semiconductor body) comprising a central portion (fig. 3, 201) and an edge portion (fig. 3 (c.f. fig. 5), 202; see [0054]-[0056] and note that the only difference between the embodiment of fig. 3 and the embodiment of fig. 5 is the inclusion of second seal ring structure 220) around at least part of the central portion (see fig. 3);
an active region arranged in the central portion (see [0033]: active chip circuity is formed within device region 201);
and a crack guiding structure (see annotated fig. 5 above) combined with a crack stop structure (fig. 5, 210; see [0036]-[0038]: the crack stop structure comprises all metal structures included within first seal ring structure 210), both being arranged in the edge portion (see fig. 5 and c.f. fig. 3),wherein the crack stop structure is asymmetric with respect to a vertical central axis through the crack stop structure (see annotated fig. 5 above; the crack stop structure (i.e. first seal ring structure 210, etc.) is asymmetric with respect to a vertical central axis passing through the crack guiding structure as there is more metal material (204, 205, etc.) on the side of the axis facing the device region 201).
Regarding claim 2, Ning discloses the electronic chip according to claim 1, wherein the crack guiding path (see annotated fig. 5 above: a crack guiding path is defined by the indicated crack guiding structure) is spatially confined at least partially inside of the crack stop structure (fig. 5, 210; the crack guiding structure of Ning defines a spatially confined crack guiding path for the propagation of a crack originating in substrate 200; [0056] confirms that first seal ring structure 210 prevents cracks from entering device region 201; thus, when a crack enters first seal ring structure 210 through the indicated crack guiding structure, the crack cannot propagate through the sub-connection layers 204a and conductive plugs 205; thus, the crack is confined to the crack guiding path within portions of dielectric layer 203 in between the component structures of first seal ring structure 210).
Regarding claim 3, Ning discloses the electronic chip according to claim 1, wherein the crack guiding structure (see annotated fig. 5 above) is configured for redirecting a propagation direction of a crack (see annotated fig. 5 above) when passing the crack guiding structure combined with the crack stop structure (fig. 5, 210; see [0079]: first seal ring structure 210 is configured as a stoppage barrier for preventing crack propagation into device region 201; an exemplary crack (see annotated fig. 5 above) will, thus, be redirected when propagating within the crack guiding structure through first seal ring structure 210).
Regarding claim 4, Ning discloses the electronic chip according to claim 1, wherein the crack guiding structure (see annotated fig. 5 above) is configured to redirect a crack (see annotated fig. 5 above) propagating towards the active region (fig. 5, 201) into an upwardly propagating crack (see annotated fig. 5 above and [0079]; since first seal ring structure 210 acts as a barrier that prevents cracks from propagating towards the device region 201, an exemplary crack starting in substrate 200 will be redirected upwards upon encountering one of the component structures of 210 such as the crack barrier section along the path defined by the crack guiding structure (as shown above)), and to further redirecting the upwardly propagating crack into a crack propagating laterally away from the active region (see annotated fig. 5 above and [0079]; since first seal ring structure 210 acts as a barrier that prevents cracks from propagating towards the device region 201, an exemplary crack that has been redirected upwards by one of the plurality of component structures of first seal ring structure 210 is further redirected into a crack propagating laterally away from the device region 201 by another component structure of 210 such as the metallic bulk structure (as shown above)).
Regarding claim 5, Ning discloses the electronic chip according to claim 1, wherein the crack stop structure (fig. 5, 210) is configured for stopping a crack, as a barrier for a crack and/or for absorbing energy of a crack (see [0079]: “[t]he seal ring structure can have vias and metal sub-connection layers in a staggered arrangement, [and] can serve as a stoppage barrier to prevent or slow down crack propagation into the device region”).
Regarding claim 6, Ning discloses the electronic chip according to claim 1, wherein the substrate (see fig. 3 and [0027]: “[t]he exemplary semiconductor structure can include a substrate 200 having a device region 201, and a seal ring region 202 surrounding the device region 201. A dielectric layer 203 can be disposed on the surface of the substrate 200”; the entire disclosed structure can be regarded as a substrate, while substrate 200 can specifically be regarded as a semiconductor body;
also see [0054]-[0056] and note that the only difference between the embodiment of fig. 3 and the embodiment of fig. 5 is the inclusion of second seal ring structure 220) comprises a semiconductor body (fig. 5, 200) with a back end of the line structure (see fig. 5 and [0004]-[0005]; the semiconductor device of Ning includes inter-layer dielectric films (e.g. dielectric layer 203) formed on substrate 200 which further encase the seal ring structures along with active wiring and contact portions; these structures can collectively be regarded as a back end of the line structure atop substrate 200 (and the chip circuit formed therein within device region 201 (see [0033]))) thereon, and wherein the crack guiding structure (see annotated fig. 5 above) combined with the crack stop structure (fig. 5, 210) form part of the back end of the line structure.
Regarding claim 7, Ning discloses the electronic chip according to claim 1, wherein the crack guiding structure (see annotated fig. 5 above) defines a dielectric path (the crack guiding structure defines a path through dielectric layer 203 within first seal ring structure 210) delimited by metallic structures (fig. 5, connection layers 204 and conductive plugs 205; see [0036]: component structures of first seal ring 210 are metallic) of the crack stop structure (fig. 5, 210), wherein in particular the dielectric path comprises a bottom-sided upward path section (see annotated fig. 5 above) merging into a top-sided lateral path section (see annotated fig. 5 above; the crack guiding structure includes (1) a bottom-sided upward path section near the interface between dielectric layer 203 and substrate 200 and (2) a top-sided lateral path section beneath the indicated metallic bulk structure of first seal ring 210).
Regarding claim 8, Ning discloses the electronic chip according to claim 1, wherein the crack stop structure (fig. 5, 210) comprises horizontal metallic structures (fig. 5, 204a; see [0036]-[0037]) and vertical metallic structures (fig. 5, 205; see [0036] and [0038]).
Regarding claim 9, Ning discloses the electronic chip according to claim 1, wherein a bottom-sided portion of the crack stop structure (see annotated fig. 5 above) comprises a crack barrier section (see annotated fig. 5 above: the crack barrier section is the indicated conductive plug 205; relative to the sacrificial section, the indicated crack barrier section faces the active device region 201) facing the active region and comprises a sacrificial section (see annotated fig. 5 above: the sacrificial section is the indicated portion of seal ring structure 210 laterally adjacent to the indicated crack barrier section and facing away from the active device region 201) facing away from the active region, wherein at least part of the crack guiding structure extends between the crack barrier section and the sacrificial section (see annotated fig. 5 above).
Regarding claim 10 (applicant is reminded of the objection of claim 10 above), Ning discloses the electronic chip according to claim 9, comprising at least one of the following features:
wherein the crack barrier section (see annotated fig. 5 above) is configured as a barrier for inhibiting propagation of a crack through the crack barrier section towards the active region (see [0079]: “The seal ring structure can have vias and metal sub-connection layers in a staggered arrangement, such that the seal ring structure can serve as a stoppage barrier to prevent or slow down crack propagation into the device region, i.e., the functional chip circuit”; note that the indicated crack barrier section in the annotated fig. 5 above comprises a component conductive plug 205 of seal ring structure 210);
and wherein the crack barrier section comprises a continuously interconnected vertical arrangement of horizontal metallic structures and vertical metallic structures (see 103 rejection of claim 21 provided below);
and wherein the sacrificial section is configured for being at least partially destroyed by a crack propagating to the crack stop structure (no grounds for rejection are expressly required by this claim limitation, but see Hudson (referenced below) fig. 8, 259, and Hudson [0039]);
and wherein the sacrificial section (see annotated Ning fig. 5 above) comprises horizontal metallic structures (see annotated fig. 5 above: sub-connection layers 204a) and vertical metallic structures (see annotated fig. 5 above: first conductive plugs 205), wherein a part of the horizontal metallic structures is interconnected with the vertical metallic structures (see fig. 5 and [0038]: only a small part of each first conductive plug is interconnected with each sub-connection layer 204a), and wherein another part of the horizontal metallic structures is separated from the vertical metallic structures (see fig. 5 and [0038]: most of each sub-connection layers 204a is separated from each first conductive plug 205).
Regarding claim 11, , Ning discloses the electronic chip according to claim 9, wherein a top-sided portion of the crack stop structure (see annotated fig. 5 above) comprises a metallic bulk structure (see annotated fig. 5 above and [0036]-[0037]; the metallic bulk structure is the indicated sub-connection layer 204a that is coplanar with a top surface of dielectric layer 203; the metallic bulk structure extends vertically from and is connected with the indicated crack barrier section;
see [0030]: “[t]he top of a first conductive plug 205 can be connected to a first connection layer 204”) extending vertically from and being connected with the crack barrier section (see annotated fig. 5 above).
Regarding claim 12, Ning discloses the electronic chip according to claim 11, wherein the metallic bulk structure (see annotated fig. 5 above) is separated by a vertical spacing (see annotated fig. 5 above; the indicated metallic bulk structure lies above the indicated sacrificial section and is separated by a vertical spacing defined by the indicated crack guiding structure) from the sacrificial section and extends laterally over at least part of the sacrificial section (see annotated fig. 5 above; the indicated metallic bulk structure extends over part of the indicated sacrificial section as shown).
Regarding claim 14, Ning discloses the electronic chip according to claim 1, comprising a seal ring (fig. 5, 220; see [0054]) arranged laterally between the active region (fig. 5, 201) on the one hand and the crack guiding structure (see annotated fig. 5 above) combined with the crack stop structure (fig. 5, 210) on the other hand (see fig. 5; second seal ring structure 220 is arranged between device region 201 and first seal ring structure 210).
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Regarding claim 15, Ning discloses the electronic chip according to claim 1, wherein the crack stop structure (fig. 5, 210; see [0036]-[0038]) comprises one or more structures having an upside-down L-shape (see annotated fig. 5 above; the indicated crack barrier section included in the crack stop structure (first seal ring structure 210, etc.) has an upside-down L-shape (i.e. a vertical portion abutted at the top side by an outward-jutting horizontal portion) in the cross-sectional view given in fig. 5 (see [0054])) in a cross-sectional view.
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Regarding claim 19, Ning discloses a manufacturing method (see [0003]), wherein the method comprises:
providing a wafer comprising a plurality of integrally connected electronic chips according to claim 1 (see [0033]; the semiconductor chip disclosed in Ning has a saw lane region and undergoes a chip sawing process whereby the chip is separated from a common wafer;
also see [0054]-[0056] and note that the only difference between the embodiment of fig. 3 and the embodiment of fig. 5 is the inclusion of second seal ring structure 220)
and separating the electronic chips from the wafer along separation lines (see [0033]) extending between adjacent edge portions of the electronic chips (fig. 5, 202; see [0033]; since the semiconductor chip of fig. 3 is cut from a common wafer as disclosed in [0033], the disclosed saw lane region lies between adjacent seal ring regions 202 of individual semiconductor chips) so that at least part of cracks created during the separating are guided along the crack guiding structures (see annotated fig. 5 above) and/or are stopped by the crack stop structures (fig. 5, 210; see [0048]: “first seal ring structure 210 can substantially completely isolate the device region 201 from the saw lane region, to better protect device region 201 and prevent the cracking or delamination generated at the saw lane region during a chip sawing process from extending into the device region 201”).
Regarding claim 20, Ning discloses the method according to claim 19, wherein the method comprises separating the electronic chips from the wafer by mechanical dicing, by laser dicing, or by another chip separation technique (see [0033]; the semiconductor chip of Ning is separated from a common wafer by mechanical dicing (i.e. “chip sawing process”)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as obvious over Ning in view of West et al. (US 20030122220 A1), hereinafter referred to as “West”.
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Ning discloses the electronic chip according to claim 1, wherein the crack stop structure (Ning fig. 5, 210) comprises a plurality of vertically stacked and mutually spaced horizontal metal structures (Ning fig. 5, 204a; see Ning [0036]-[0037]; [0036] discloses that first seal ring structure 210 is composed of metal, so sub-connection layers 204a are metal structures; [0037] discloses (and fig. 5 confirms) that sub-connection layers 204a are arranged vertically (i.e. stacked) in a staggered formation (with overlapping partial vertical alignment); see annotated Ning fig. 5 above and note that the indicated plurality of sub-connection layers 204a are mutually spaced in that there is a regular spacing between the vertically adjacent layers by nature of the layers’ parallel surfaces).
Ning fails to disclose wherein the horizontal metal structures have a thickness which increases from bottom to top of the crack stop structure.
West discloses seal ring structures (see West fig. 1A) for inhibiting the propagation of cracks in integrated circuit (IC) chips caused by wafer dicing (see West [0037]-[0042]) wherein the seal ring structures comprise a plurality of vertically stacked and mutually spaced horizontal metal structures (West fig. 1A, 120; see West [0061] and note that electrically conductive layers 120 are composed of metal; West fig. 1A shows a plurality electrically conductive layers 120 that are vertically stacked and mutually spaced in that there is a regular spacing between any given pair of vertically adjacent layers by nature of the layers’ parallel surfaces) having a thickness which increases from bottom to top of the crack stop structure (see West fig. 1A: the seal ring structure in seal region 104 can be regarded as a crack stop structure; see West [0061] and fig. 1A: “several layers [120] may typically be in the thickness range between about 0.4 and 0.7 .mu.m, while later depositions may have an increased thickness from about 0.8 to 1.2 .mu.m”; note that this increasing thickness from bottom (earlier deposition layers) to top (later deposition layers) is shown in West fig. 1A).
The bottom-to-top increasing thickness teachings of West are incorporated into the crack stop structure of Ning wherein the combination discloses a plurality of vertically stacked and mutually spaced horizontal metal structures having a thickness which increases from bottom to top of the crack stop structure.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the crack stop structure of Ning with the increasing thickness teachings of West to reduce the amount of metallic deposition material used in fabricating the crack stop structure while maintaining robust crack-inhibiting functionality.
Claims 16-17 are rejected under 35 U.S.C. 103 as obvious over Ning in view of Jeng et al. (US 20090115024 A1), hereinafter referred to as “Jeng”.
Regarding claim 16, Ning discloses the electronic chip according to claim 1.
Ning fails to disclose the chip comprising at least one crack propagation inhibiting trench formed in the substrate and being configured for inhibiting horizontal propagation of a crack.
Jeng discloses a semiconductor chip (see Jeng fig. 4A and [0009]) with a seal ring structure (Jeng fig. 4A, seal rings 42 and 44; see Jeng [0025]), wherein the semiconductor chip comprises at least one crack propagation inhibiting trench (Jeng fig. 4A, 66; see Jeng [0034]) formed in the substrate (see Jeng fig. 4A; the substrate includes semiconductor substrate 30 (which can be regarded as a semiconductor body), ILD 34, low-k dielectric layers 50, top dielectric layer 52, first passivation layer Pass-1, and second passivation layer Pass-2) and being configured for inhibiting horizontal propagation of a crack (see Jeng [0035]: “bottom 68 of trench 66 may also be below interface 62, or at other positions as shown in dashed lines. Advantageously, with bottom 68 below interface 62, the cracks propagated along interface 62 may be stopped”; also see Jeng fig. 4A and note that a crack propagating along interface 62 would be substantially horizontal).
The crack propagation inhibiting trench of Jeng is incorporated into the semiconductor chip of Ning.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the trench propagation inhibiting trench teachings of Jeng into the semiconductor chip of Ning to release the stress imparted by certain horizontally propagating cracks (see Jeng [0033]; also see [0034]-[0035] and note that the only substantial difference between the embodiment of fig. 3B and the embodiment of fig. 4A is the location of trench 66).
Regarding claim 17, Ning and Jeng disclose the electronic chip according to claim 16, comprising at least one of the following features:
wherein the at least one crack propagation inhibiting trench is formed so that the crack guiding structure combined with the crack stop structure are arranged laterally between the at least one crack propagation inhibiting trench on the one hand and the active region on the other hand (no grounds for rejection are expressly required by this limitation, but see Jeng fig. 4A and [0038]);
and wherein the at least one crack propagation inhibiting trench is arranged laterally between the crack guiding structure combined with the crack stop structure on the one hand and a seal ring on the other hand (no grounds for rejection are expressly required by this limitation, but see Jeng fig. 4B and [0035]);
and wherein the at least one crack propagation inhibiting trench is arranged laterally between the crack guiding structure combined with the crack stop structure on the one hand and the active region on the other hand (no grounds for rejection are expressly required by this limitation, but see Jeng fig. 4B and [0035]);
and wherein the at least one crack propagation inhibiting trench (Jeng fig. 4A, 66; see Jeng [0034]) is formed at least partially in a passivation layer (Jeng fig. 4A, Pass-2; see Jeng [0027]) of the substrate (see Jeng fig. 4A; the substrate includes semiconductor substrate 30 (which can be regarded as a semiconductor body), ILD 34, low-k dielectric layers 50, top dielectric layer 52, first passivation layer Pass-1, and second passivation layer Pass-2), in particular extending into a back end of the line dielectric (Jeng fig. 4A, 52; see [0026]; also see [0002] and note that invention of Jeng relates to the “back end” stage of semiconductor chip fabrication) of the substrate below the passivation layer (see Jeng fig. 4A and [0034]: “the bottom 68 of trench 66 may extend below the interface 62 [between first passivation layer Pass-1 and top dielectric layer 52]”).
Claim 18 and 21-22 are rejected under 35 U.S.C. 103 as obvious over Ning in view of Hudson (US 20110068435 A1), hereinafter referred to as “Hudson”.
Regarding claim 18, Ning discloses an electronic chip according to claim 1.
Ning fails to disclose a package, comprising: a carrier; said electronic chip mounted on the carrier; and an encapsulant encapsulating at least part of the electronic chip and the carrier.
Hudson discloses a semiconductor chip package (Hudson fig. 1; see Hudson [0024]), comprising:
a carrier (Hudson fig. 1, 20);
an electronic chip (Hudson fig. 1, 15) mounted on the carrier;
and an encapsulant (Hudson fig. 1, 30; see Hudson [0027] and fig. 11: underfill material 30 is composed of epoxy resin and encapsulates part of chip 15 and carrier substrate 20) encapsulating at least part of the electronic chip and the carrier.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the chip package teachings of Hudson with the semiconductor chip taught in Ning to protect the semiconductor chip from further environmental damage such as moisture damage.
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Regarding claim 21, Ning discloses the electronic chip of claim 1, wherein:
the substrate (see fig. 3 and [0027]: “[t]he exemplary semiconductor structure can include a substrate 200 having a device region 201, and a seal ring region 202 surrounding the device region 201. A dielectric layer 203 can be disposed on the surface of the substrate 200”; the entire disclosed structure can be regarded as a substrate, while substrate 200 can specifically be regarded as a semiconductor body) comprises:
a semiconductor body (Ning fig. 5, 200) and a back end of the line (BEOL) dielectric (Ning fig. 5, 203; see [0028]) structured thereon;
and the crack stop structure (Ning fig. 5, 210) comprises:
a crack barrier section (see annotated Ning fig. 5 above) comprising an arrangement of horizontal and vertical metallic structures (see Ning fig. 5 and [0036]-[0039]: first seal ring structure 210 comprises an arrangement of vertical first conductive plugs 205 and horizontal sub-connection layers 204a (both metallic structures) extending through the vertical thickness of dielectric layer 203) extending through the vertical thickness of the BEOL dielectric;
and a sacrificial section (see annotated Ning fig. 5 above) comprising horizontal and vertical metallic structures (see Ning fig. 5 and [0036]-[0039]: the sacrificial section comprises vertical first conductive plugs 205 and horizontal sub-connection layers 204a (both metallic structures) extending partially through the vertical thickness of dielectric layer 203) extending partially through the vertical thickness of the BEOL dielectric and separated from the crack barrier section to define therebetween at least part of the crack guiding structure (see annotated Ning fig. 5 above) in the form of a crack propagation path (see annotated Ning fig. 5 above: a crack propagation path is defined by the crack guiding structure between the crack barrier section and the sacrificial section) through the BEOL dielectric.
Ning fails to disclose the crack stop structure comprising a crack barrier section comprising a continuously interconnected vertical arrangement of horizontal and vertical metallic structures extending through the vertical thickness of the BEOL dielectric.
Hudson discloses a crack barrier section (Hudson fig. 4, 50; see [0032]; c.f. fig. 11) comprising a continuously interconnected vertical arrangement of horizontal and vertical metallic structures (see Hudson fig. 4, [0032], and [0035]: crack deflection structure 50 comprises a continuously interconnected vertical arrangement of metallic horizontal interconnect layers (140, 150, 160, 170, etc.) and vertical vias (145, 155, 165, 175)) extending through the vertical thickness of a BEOL dielectric (Hudson fig. 4, insulating material layers (110, 115, 120, 125, and 130); see [0038] which confirms that the insulating layers are dielectric).
The crack barrier section of Hudson is incorporated as the crack barrier section of the electronic chip of Ning wherein the combination discloses all of the limitations of claim 21.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ning with the crack barrier section of Hudson to more reliably prevent cracks from penetrating the crack stop structure and, thus, more reliably protect the active region.
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Regarding claim 22, Ning and Hudson disclose the electronic chip of claim 21, wherein the crack barrier section (Hudson fig. 4, 50; c.f. Hudson fig. 11; in the combined device, the crack barrier section is located as indicated in the above annotated Ning fig. 5) and sacrificial section (see annotated Ning fig. 5 above) are vertically adjacent to one another (see annotated Ning fig. 5 above) to define a vertical portion of the crack propagation path (see annotated Ning fig. 5 above) and overlap vertically with one another (see annotated Ning fig. 5 above) to define a horizontal portion of the crack propagation path (see annotated Ning fig. 5 above).
Response to Arguments
Applicant’s arguments filed May 6th, 2026, have been fully considered. The majority of said arguments have been found unpersuasive.
On page 8 of applicant’s response, Applicant suggests that the present amendments to claims 10, 15, and 17 overcome the respective 112(b) rejections presented in the previous Office Action. Aside from the objection to claim 10 given above, Examiner agrees and the previous 112(b) rejections are withdrawn.
On page 9 of applicant’s response, Applicant submits that the art of record fails to teach or suggest the amended limitation of claim 1 regarding the crack stop structure being asymmetric with respect to a vertical central axis through said structure. Accordingly, Applicant suggests that the 102 rejection of claim 1 should be withdrawn. Examiner respectfully disagrees with this line of reasoning. As shown above, the crack stop structure as taught by Ning is asymmetric with respect to a vertical central axis in that more metallic structure is disposed on the left side of the vertical central axis than on the right side. Therefore, the 102 rejection of amended independent claim 1 is maintained.
Applicant further suggests that the 102 rejection of claim 19 should be withdrawn because claim 19 includes the limitations of independent claim 1. Examiner disagrees: claim 19 is anticipated by Ning as shown in the 102 rejection above. Furthermore, claim 19 is not allowable based on its inclusion of the limitations of claim 1 because claim 1 is also anticipated by Ning as shown above.
On page 9 of applicant’s response, it seems as if Applicant’s remarks were cut off or otherwise left incomplete. Applicant is encouraged to further clarify the missing arguments in subsequent stages of prosecution. The 102 rejections of claims 2-12 and 14 over Ning are maintained because independent claim 1 remains anticipated by Ning.
On page 10 of applicant’s response, Applicant submits that the 103 rejection of claim 18 over Ning in view of Hudson be withdrawn because (1) the amended limitations of independent claim 1 are patentable over Ning (and Sinha) and (2) the teachings of Hudson fail to remedy the deficiencies of Ning with respect to claim 18. As explained above, Examiner respectfully disagrees that Ning fails to teach or suggest a crack stop structure being asymmetric with respect to a vertical central axis through said structure (i.e. the amended limitation of claim 1 from previous claim 15). Therefore, the 103 rejection of claim 18 is maintained.
On page 10, Applicant further suggests that the 103 rejections of claims 13 and 15-17 should be withdrawn due to their dependence on independent claim 1. As explained above, claim 1 remains anticipated by Ning. Therefore, the 103 rejections of claims 13 and 15-17 are maintained.
On page 10, Applicant suggests that amended claim 15 is independently allowable over the art of record because said art fails to teach or suggest the limitation whereby the crack stop structure comprises one or more structures having an upside-down L-shape in a cross-sectional view. Examiner is unpersuaded by this suggestion. Examiner has shown in the rejection above that Ning does in fact disclose the crack stop structure comprising one or more structures having an upside-down L-shape (i.e. a vertical portion abutted at the top side by an outward-jutting horizontal portion) in a cross-sectional view. As such, claim 15 is hereby anticipated by Ning and rejected under 102(a)(1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Steven Loke whose telephone number is (571)272-1657. The examiner can normally be reached Monday to Friday, 8:30 am to 6 pm.
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/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights