Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 11, 2023 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 were rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. All the independent claims, claim 1, claim 17 & claim 19, recite a blocking layer, wherein the blocking layer comprises “a plurality of active blocking portions contacting the plurality of active layers, respectively; and at least one first bent portion bent and extending from at least one of the plurality of active blocking portions and contacting the gate spacer”. The specification of the instant application has not defined the meaning of the word “bent”. Without any guidance, it is difficult for a person of ordinary skill in the art to determine the metes and bounds of the term “bent”, whether a slightly tapered or curved or faceted surface qualifies as “bent”. Appropriate correction/clarification is requested.
Claims 2-16, 18 & 20 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112, 2nd paragraph (pre-AIA ) rejections based on their dependencies on claims 1, 17 & 19.
Claim 2 recites, inter alia, “… wherein the at least one first bent portion comprises a vertical bent portion extending from an upper active blocking portion among the plurality of active blocking portions and contacting the gate spacer.” The specification of the instant application has not defined the meaning of the word “vertical bent portion”. Without any guidance, it is difficult for a person of ordinary skill in the art to determine the metes and bounds of the term “vertical bent portion”. Appropriate correction/clarification is requested. Claims 3-10 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112, 2nd paragraph (pre-AIA ) rejections based on their dependency on claim 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. (Pub. No.: US 2020/0220015 A1).
Regarding Claim 1, Jang et al. discloses a semiconductor device, comprising: an active region comprising a first portion and a second portion (Par. 0077, 0097; Fig. 10 – active region 105; the portion of the active region under the channel structure 140 could be considered as the first portion; the portion of the active region under the source/drain region 150f could be considered as the second portion); an isolation region on a side surface of the active region (Par. 0077, 0097; Fig. 10 – isolation region 110); a plurality of active layers stacked and spaced apart from each other in a vertical direction, and on the first portion of the active region (Par. 0077, 0097; Fig. 10 – plurality of active layers (channel layers) 141, 142, 143); an epitaxial structure disposed on the second portion of the active region, connected to the plurality of active layers, and overlapping the isolation region in the vertical direction (Par. 0077, 0097; Fig. 10 –epitaxial structure comprising source/drain region 150f);
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a gate structure surrounding the plurality of active layers (Par. 0077, 0097, 0101; Fig. 10 – gate structure comprising gate electrode 165); and a gate spacer on a side surface of the gate structure (Par. 0077, 0097; 0103; Fig. 10 – gate spacer comprising spacers 164 & 130), wherein the epitaxial structure comprises a blocking layer and a source/drain structure on the blocking layer (Par. 0077, 0097 -0098; Fig. 10 – blocking layer 152f (first epitaxial layer); source/drain structure 154f (second epitaxial layer), and wherein the blocking layer comprises: a plurality of active blocking portions contacting the plurality of active layers, respectively (Par. 0097; Fig. 10); and at least one first bent portion bent and extending from at least one of the plurality of active blocking portions and contacting the gate spacer (Par. 0097; Fig. 10).
Regarding Claim 2, Jang et al., as applied to claim 1, discloses
the semiconductor device, wherein the at least one first bent portion comprises a vertical bent portion extending from an upper active blocking portion among the plurality of active blocking portions and contacting the gate spacer (Par. 0097; Fig. 10).
Regarding Claim 3, Jang et al., as applied to claim 2, discloses
the semiconductor device, wherein the gate spacer comprises an internal side surface contacting the gate structure, an external side surface opposite to the internal side surface, and a lower surface contacting an upper surface of the upper active blocking portion (Par. 0097; Fig. 10), and wherein the vertical bent portion contacts a portion of the external side surface of the gate spacer (Par. 0097; Fig. 10 – gate spacer 164).
Regarding Claim 4, Jang et al., as applied to claim 3, discloses
the semiconductor device, wherein the plurality of active layers comprise an upper active layer (Par. 0097; Fig. 10), wherein the gate spacer comprises a first spacer and a second spacer (Par. 0097; Fig. 10 – first spacer 164, second spacer 190 (BRI)), wherein the first spacer comprises a vertical portion between the second spacer and the gate structure, and a lower portion between the second spacer and the upper active layer (Par. 0097; Fig. 10), and wherein the vertical bent portion contacts the first spacer (Par. 0097; Fig. 10 – gate spacer 164).
Regarding Claim 5, Jang et al., as applied to claim 4, discloses
the semiconductor device, wherein the vertical bent portion is spaced apart from the second spacer (Par. 0097; Fig. 10 – under BRI, only the upper half of insulating layer 190 could be considered as the second spacer; under this definition of the second spacer layer, the limitation is read as the vertical bent portion only contacts the very bottom of the insulating layer).
Regarding Claim 17, Jang et al. discloses a semiconductor device, comprising: an active region comprising a first portion and a second portion (Par. 0077, 0097; Fig. 10 – active region 105; the portion of the active region under the channel structure 140 could be considered as the first portion; the portion of the active region under the source/drain region 150f could be considered as the second portion); an isolation region on a side surface of the active region (Par. 0077, 0097; Fig. 10 – isolation region 110); a plurality of active layers stacked and spaced apart from each other in a vertical direction and on the first portion of the active region (Par. 0077, 0097; Fig. 10 – plurality of active layers (channel layers) 141, 142, 143); an epitaxial structure disposed on the second portion of the active region, connected to the plurality of active layers, and overlapping the isolation region in the vertical direction (Par. 0077, 0097; Fig. 10 –epitaxial structure comprising source/drain region 150f);
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a gate structure surrounding the plurality of active layers (Par. 0077, 0097, 0101; Fig. 10 – gate structure comprising gate electrode 165); and a gate spacer on a side surface of the gate structure (Par. 0077, 0097; 0103; Fig. 10 – gate spacer comprising spacers 164 & 130), wherein the gate structure includes: a plurality of lower gate portions below the plurality of active layers, respectively (Fig. 10); and an upper gate portion on an upper active layer among the plurality of active layers (Fig. 10), wherein the epitaxial structure comprises a blocking layer and a source/drain structure on the blocking layer (Par. 0077, 0097 -0098; Fig. 10 – blocking layer 152f (first epitaxial layer); source/drain structure 154f (second epitaxial layer), and wherein the blocking layer comprises: a lower blocking portion contacting the second portion of the active region (Par. 0097; Fig. 10); a plurality of active blocking portions contacting the plurality of active layers, respectively (Par. 0097; Fig. 10); a plurality of gate blocking portions contacting the lower gate portions, respectively (Par. 0097; Fig. 10); and at least one bent portion bent and extending from at least one of the plurality of active blocking portions, the plurality of gate blocking portions, and the lower blocking portion, and contacting the gate spacer (Par. 0097; Fig. 10).
Regarding Claim 18, Jang et al., as applied to claim 17, discloses
the semiconductor device, wherein the blocking layer comprises a silicon layer, and wherein the source/drain structure comprises a silicon germanium layer (Par. 0094-0097 in light of the disclosures of Par. 0029-0030; Fig. 10 – although it is not disclosed explicitly, it has been implied as a possibility).
Regarding Claim 19, Jang et al. discloses a semiconductor device, comprising: an active region comprising a first portion and a second portion (Par. 0077, 0097; Fig. 10 – active region 105; the portion of the active region under the channel structure 140 could be considered as the first portion; the portion of the active region under the source/drain region 150f could be considered as the second portion);
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a plurality of active layers stacked and spaced apart from each other in a vertical direction and on the first portion of the active region (Par. 0077, 0097; Fig. 10 – plurality of active layers (channel layers) 141, 142, 143); an epitaxial structure on the second portion of the active region and connected to the plurality of active layers (Par. 0077, 0097; Fig. 10 –epitaxial structure comprising source/drain region 150f); a gate structure surrounding the plurality of active layers (Par. 0077, 0097, 0101; Fig. 10 – gate structure comprising gate electrode 165); and a gate spacer on a side surface of the gate structure (Par. 0077, 0097; 0103; Fig. 10 – gate spacer comprising spacers 164 & 130), wherein the gate structure comprises: a plurality of lower gate portions below the plurality of active layers, respectively (Fig. 10); and an upper gate portion above an upper active layer among the plurality of active layers (Fig. 10), wherein the epitaxial structure comprises a blocking layer and a source/drain structure on the blocking layer (Par. 0077, 0097 -0098; Fig. 10 – blocking layer 152f (first epitaxial layer); source/drain structure 154f (second epitaxial layer), and wherein the blocking layer comprises: a lower blocking portion contacting the second portion of the active region (Fig. 10); a plurality of active blocking portions contacting the plurality of active layers, respectively (Par. 0097; Fig. 10); a plurality of gate blocking portions contacting the lower gate portions, respectively (Par. 0097; Fig. 10); and at least one bent portion bent and extending horizontally from at least one of the plurality of active blocking portions and the plurality of gate blocking portions and contacting the gate spacer (Par. 0097; Fig. 10).
Regarding Claim 20, Jang et al., as applied to claim 19, discloses
the semiconductor device, wherein the blocking layer comprises a silicon layer doped with at least one of carbon (C), oxygen (O), nitrogen (N), and fluorine (F) (Par. 0094-0097 in light of the disclosures of Par. 0029-0030; Fig. 10 – the blocking layer comprises a silicon layer potentially doped with carbon (C)), wherein the source/drain structure comprises a silicon germanium layer having p-type conductivity (Par. 0094-0097 in light of the disclosures of Par. 0029-0030; Fig. 10 – although it is not disclosed explicitly, it has been implied as a possibility), and wherein a thickness of the blocking layer is in a range of about 1 nm to about 5 nm (Par. 0031).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chung et al. (Pub. No.: US 2020/0381530 A1) – This prior art teaches a semiconductor comprising: an active region comprising a first portion and a second portion; an isolation region on a side surface of the active region; a plurality of active layers stacked and spaced apart from each other in a vertical direction, and on the first portion of the active region; an epitaxial structure disposed on the second portion of the active region, connected to the plurality of active layers, and overlapping the isolation region in the vertical direction; a gate structure surrounding the plurality of active layers; and a gate spacer on a side surface of the gate structure, wherein the epitaxial structure comprises a blocking layer and a source/drain structure on the blocking layer, and wherein the blocking layer comprises: a plurality of active blocking portions contacting the plurality of active layers, respectively; and Fig. 19B).
Peng et al. (Pub. No.: US 2020/0168716 A1) – This prior art teaches a semiconductor comprising: an active region comprising a first portion and a second portion; an isolation region on a side surface of the active region; a plurality of active layers stacked and spaced apart from each other in a vertical direction, and on the first portion of the active region; an epitaxial structure disposed on the second portion of the active region, connected to the plurality of active layers, and overlapping the isolation region in the vertical direction; a gate structure surrounding the plurality of active layers; and a gate spacer on a side surface of the gate structure, wherein the epitaxial structure comprises a blocking layer and a source/drain structure on the blocking layer, and wherein the blocking layer comprises: a plurality of active blocking portions contacting the plurality of active layers, respectively; and at least one first bent portion bent and extending from at least one of the plurality of active blocking portions and contacting the gate spacer (Fig. 13).
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12/06/2025
/SYED I GHEYAS/Primary Examiner, Art Unit 2893