DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Note by the Examiner For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis. Election/Restrictions Claims 20-23 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 13, 2026. Claim Objections Claims 2, 4, 6, 8, and 10-11 are objected to because of the following informalities: Regarding claim 2 , “ lenth ” should be corrected to “length ”; Regarding claim 4 , “ comrpising ” should be corrected to “comprising ”; Regarding claim 6 , “ comrpising ” should be corrected to “comprising ”; Regarding claim 8 , “ comrising ” should be corrected to “comprising ”; Regarding claim 10 , “ lenth ” should be corrected to “length ”; Regarding claim 11 , “ plural tiy ” should be corrected to “plurality”. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application , as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 , 3-9, 11, and 15 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Xie et al. ( US 20220406715 A1 ), hereinafter referred to as “Xie” . Regarding claim 1 , Xie discloses a semiconductor device (see fig. 14A; see [0024] and [0086] -[ 0087]: semiconductor structure 100 is part of a stacked FET device) comprising: a 1st source/drain region (fig. 14B, 1210; see [00 77 ] : note that the bottom source/drain region 1210 is connected to channel layers 18 via epitaxial growth therefrom ; note that the orientation of semiconductor structure 100 as shown in figs. 14A-B is flipped relative to page orientation such that backside regions (bottom, etc.) are shown above frontside (top, etc.) regions; also see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A ; see [0007]-[0020]: figs. 1-14D show intermediate steps in the fabrication of the same semiconductor structure 100 ) connected to a 1 s t channel structure ( see fig. 9A and [ 0071]-[0072]: the first channel structure comprises the channel layers 18 that are disposed below middle dielectric layer (MDL) 52 ) ; a 2nd source/drain region ( fig. 13B, 80; c.f. fig. 14A ; see [0067] : note that the top source/drain region 80 is connected to channel layers 18 via epitaxial growth therefrom ) , above the 1st source/drain region, connected to a 2nd channel structure ( see fig. 9A and [0071]-[0072]: the second channel structure comprises the channel layers 18 that are disposed above middle dielectric layer (MDL) 52 ) above the 1st channel structure; a backside contact structure ( fig. 14A, 1300; see [0080] -[ 0083]; see [0085]: backside local interconnect 1300 “ may provide an electrical signal or power supply to the bottom source/drain region 1210 ”; contact 1300 thus connects bottom source/drain region 1210 on a bottom surface thereof ) on a bottom surface of the 1st source/drain region; and a backside isolation structure ( fig. 14B, 12; see [0087] and c.f. fig. 14A; insulator layer 12 surrounds backside local interconnect 1300 ) surrounding the backside contact structure, wherein the bottom surface of the 1st source/drain region is at a level below a top surface of the backside isolation structure ( see fig. 14A and c.f. fig. 14B; applicant is reminded of the flipped orientation of semiconductor structure 100 relative to the page; the bottom surface of the bottom source/drain region 1210 is at a level below a top surface of insulator layer 12 ) . Regarding claim 3 , Xie discloses t he semiconductor device of claim 1, further comprising a gate structure (fig. 10A, 92; see [0072] ; see [0007]-[0020]: figs. 1-14D show intermediate steps in the fabrication of the same semiconductor structure 100 ) surrounding the 1st channel structure ( see fig. 9A and [0071]-[0072]: the first channel structure comprises the channel layers 18 that are disposed below middle dielectric layer (MDL) 52; replacement metal gate 92 surrounds channel layers 18 ) , wherein the bottom surface of the 1st source/drain region (fig. 14B, 1210; also see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A) is at a level below a bottom surface of the gate structure ( see fig. 14A , c.f. fig. 12A ; applicant is reminded of the flipped orientation of semiconductor structure 100 relative to the page; the bottom surface of the bottom source/drain region 1210 is at a level below a bottom surface of replacement metal gate 92 ) . Regarding claim 4 , Xie discloses t he semiconductor device of claim 1, further comprising : a gate structure (fig. 10A, 92; see [0072]; see [0007]-[0020]: figs. 1-14D show intermediate steps in the fabrication of the same semiconductor structure 100) surrounding the 1st channel structure (see fig. 9A and [0071]-[0072]: the first channel structure comprises the channel layers 18 that are disposed below middle dielectric layer (MDL) 52; replacement metal gate 92 surrounds channel layers 18) which comprises a plurality of channel layers (fig. 10A, 18) vertically stacked and extended in a channel-length direction (see fig. 10A) ; and a plurality of inner spacers (fig. 10A, 64; c.f. fig. 14A: inner spacers 64 are disposed between the bottom source/drain region 1210 and the replacement metal gate 92 in a channel length direction as shown in the annotated figure above ; see [0060] ) , wherein the gate structure is formed between the channel layers ( see [0072]: replacement metal gate 92 fills the cavities between channel layers 18 ) , wherein the inner spacers are formed between the 1st source/drain region (fig. 14B, 1210; also see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A) and the gate structure formed between the channel layers ( see annotated fig. 14A above; inner spacers 64 (c.f. fig. 10A) are formed between the bottom source/drain region 1210 and the replacement metal gate 92 between the channel layers 18 in a channel length direction ) , and wherein the bottom surface of the 1st source/drain region is at a level below a bottom surface of the lowermost inner spacer among the inner spacers ( see annotated fig. 14A above; applicant is reminded of the flipped orientation of semiconductor structure 100 relative to the page; the bottom surface of the bottom source/drain region 1210 is at a level below a bottom surface of the lowermost inner spacer among inner spacers 64 ) . Regarding claim 5 , Xie discloses t he semiconductor device of clam 4, wherein the bottom surface of the 1st source/drain region ( fig. 14B, 1210; also see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A ) is at a level below a bottom surface of the gate structure ( fig. 10A, 92; see [0072]; see [0007]-[0020]: figs. 1-14D show intermediate steps in the fabrication of the same semiconductor structure 100; see fig. 14A c.f. fig. 12A; applicant is reminded of the flipped orientation of semiconductor structure 100 relative to the page; the bottom surface of the bottom source/drain region 1210 is at a level below a bottom surface of replacement metal gate 92 ) . Regarding claim 6 , Xie discloses t he semiconductor device of claim 1, further comprising : a gate structure (fig. 10A, 92; see [0072]; see [0007]-[0020]: figs. 1-14D show intermediate steps in the fabrication of the same semiconductor structure 100) surrounding the 1st channel structure (see fig. 9A and [0071]-[0072]: the first channel structure comprises the channel layers 18 that are disposed below middle dielectric layer (MDL) 52; replacement metal gate 92 surrounds channel layers 18) which comprises a plurality of channel layers (fig. 10A, 18) vertically stacked and extended in a channel-length direction (see fig. 10A) ; and a plurality of inner spacers (fig. 10A, 64; c.f. fig. 14A: inner spacers 64 are disposed between the bottom source/drain region 1210 and the replacement metal gate 92 in a channel length direction as shown in the annotated figure above ; see [0060] ) , wherein the gate structure is formed between the channel layers ( see [0072]: replacement metal gate 92 fills the cavities between channel layers 18 ) , wherein the inner spacers are formed between the 1st source/drain region ( fig. 14B, 1210; also see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A ) and the gate structure formed between the channel layers (see fig. 14A: inner spacers 64 (c.f. fig. 10A) are formed between the bottom source/drain region 1210 and the replacement metal gate 92 between the channel layers 18 in a channel length direction) , and wherein a top surface of the 1st source/drain region is at a level on or below a top surface of the uppermost lower inner spacer ( see annotated fig. 14A above; applicant is reminded of the flipped orientation of semiconductor structure 100 relative to the page orientation ; a top surface of the bottom source/drain region 1210 is at a level below a top surface of the uppermost lower inner spacer among the inner spacers 64 ) . Regarding claim 7 , Xie discloses t he semiconductor device of claim 1, further comprising: a frontside isolation structure ( see fig. 12A and c.f. fig. 14A; see [0065]: “ ILD 72 could comprise with dielectric materials such as SiO2, SiN , SiC , SiCO , or combination of those materials ”; inter-layer dielectric (ILD) 72 thus comprises multiple dielectric layers, the top one of which is a frontside isolation structure as shown in the ann otated fig. 14A above (the frontside isolation structure is disposed on top of the passivation structure as shown above) ; see [0007]-[0020]: figs. 1-14D show intermediate steps in the fabrication of the same semiconductor structure 100 ) between the 1st source/drain region ( fig. 12A, 1210; c.f. fig. 14A: the indicated frontside isolation structure within ILD 72 is disposed between bottom source/drain region 1210 and top source/drain region 80 ) and the 2 n d source/drain region ( fig. 12A, 80; c.f. fig. 14A ) ; and a passivation structure ( see fig. 12A and c.f. fig. 14A; see [0065]: “ ILD 72 could comprise with dielectric materials such as SiO2, SiN , SiC , SiCO , or combination of those materials ”; inter-layer dielectric (ILD) 72 thus comprises multiple dielectric layers, the bottom one of which is a passivation structure as shown in the annotated fig. 14A above (the passivation structure is disposed below the frontside isolation structure as shown above) ) between the 1st source/drain region and the frontside isolation structure (see annotated fig. 14A above and c.f. fig. 12A) . Regarding claim 8 , Xie discloses t he semiconductor device of claim 7, further comprising : a gate structure (fig. 10A, 92; see [0072]; see [0007]-[0020]: figs. 1-14D show intermediate steps in the fabrication of the same semiconductor structure 100) surrounding the 1st channel structure (see fig. 9A and [0071]-[0072]: the first channel structure comprises the channel layers 18 that are disposed below middle dielectric layer (MDL) 52; replacement metal gate 92 surrounds channel layers 18) which comprises a plurality of channel layers (fig. 10A, 18) vertically stacked and extended in a channel-length direction (see fig. 10A) ; and a plurality of inner spacers (fig. 10A, 64; c.f. fig. 14A: inner spacers 64 are disposed between the bottom source/drain region 1210 and the replacement metal gate 92 in a channel length direction as shown in the annotated figure above ; see [0060] ) , wherein the gate structure is formed between the channel layers ( see [0072]: replacement metal gate 92 fills the cavities between channel layers 18 ) , wherein the inner spacers are formed between the 1st source/drain region ( fig. 14B, 1210; also see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A ) and the gate structure formed between the channel layers ( see fig. 14A: inner spacers 64 (c.f. fig. 10A) are formed between the bottom source/drain region 1210 and the replacement metal gate 92 between the channel layers 18 in a channel length direction ) , and wherein the passivation structure ( see fig. 12A and c.f. fig. 14A; see [0065]: “ ILD 72 could comprise with dielectric materials such as SiO2, SiN , SiC , SiCO , or combination of those materials ”; inter-layer dielectric (ILD) 72 thus comprises multiple dielectric layers, the bottom one of which is a passivation structure as shown in the annotated fig. 14A above ) is formed on a side surface of at least a portion of the uppermost inner spacer among the inner spacers ( see the annotated fig. 14A above; the indicated passivation structure is formed on a portion of the indicated uppermost inner spacer among the indicated inner spacers 64 ) . Regarding claim 9 , Xie discloses a semiconductor device comprising: a 1st source/drain region ( fig. 14B, 1210; see [0077]: note that the bottom source/drain region 1210 is connected to channel layers 18 via epitaxial growth therefrom; note that the orientation of semiconductor structure 100 as shown in figs. 14A-B is flipped relative to page orientation such that backside regions (bottom, etc.) are shown above frontside (top, etc.) regions; also see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A ; see [0007]-[0020]: figs. 1-14D show intermediate steps in the fabrication of the same semiconductor structure 100 ) connected to a 1st channel structure ( see fig. 9A and [0071]-[0072]: the first channel structure comprises the channel layers 18 that are disposed below middle dielectric layer (MDL) 52 ) ; a passivation structure ( see fig. 12A and c.f. fig. 14A; see [0065]: “ ILD 72 could comprise with dielectric materials such as SiO2, SiN , SiC , SiCO , or combination of those materials ”; inter-layer dielectric (ILD) 72 thus comprises multiple dielectric layers, the bottom one of which is a passivation structure as shown in the annotated fig. 14A above (the passivation structure is disposed below the frontside isolation structure as shown above) ) on the 1st source/drain region; a frontside isolation structure ( see fig. 12A and c.f. fig. 14A; see [0065]: “ ILD 72 could comprise with dielectric materials such as SiO2, SiN , SiC , SiCO , or combination of those materials ”; inter-layer dielectric (ILD) 72 thus comprises multiple dielectric layers, the top one of which is a frontside isolation structure as shown in the annotated fig. 14A above (the frontside isolation structure is disposed on top of the passivation structure as shown above) ) on the passivation structure; a 2nd source/drain region ( fig. 13B, 80; c.f. fig. 14A; see [0067]: note that the top source/drain region 80 is connected to channel layers 18 via epitaxial growth therefrom ) , on the frontside isolation structure, connected to a 2nd channel structure ( see fig. 9A and [0071]-[0072]: the second channel structure comprises the channel layers 18 that are disposed above middle dielectric layer (MDL) 52 ) above the 1st channel structure; a gate structure ( fig. 10A, 92; see [0072]; c.f. fig. 14A ) surrounding the 1st channel structure and the 2nd channel structure ( see fig. 9A and [0071] -[ 0072]: replacement metal gate 92 surrounds channel layers 18 both below (i.e. first channel structure) and above (i.e. second channel structure) the middle layer dielectric ( MDL ) 52; c.f. fig. 14A ) ; a backside contact structure ( fig. 14A, 1300; see [0080] -[ 0083]; see [0085]: backside local interconnect 1300 “ may provide an electrical signal or power supply to the bottom source/drain region 1210 ”; contact 1300 thus connects bottom source/drain region 1210 on a bottom surface thereof ) on a bottom surface of the 1st source/drain region; and a backside isolation structure ( fig. 14B, 12; see [0087] and c.f. fig. 14A ) surrounding the backside contact structure (see fig. 14B c.f. fig. 14A: insulator layer 12 surrounds backside local interconnect 1300) . Regarding claim 11 , Xie discloses t he semiconductor device of claim 9, further comprising: a plurality of inner spacers ( fig. 10A, 64; c.f. fig. 14A: indicated inner spacers 64 are disposed between the bottom source/drain region 1210 and the replacement metal gate 92 in a channel length direction as shown in the annotated figure above; see [0060]; also see [0007]-[0020]: note that figs. 1-14D show intermediate steps in the fabrication of the same semiconductor structure 100 ) formed between the 1st source/drain region ( fig. 14B, 1210; also see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A ) and the gate structure ( fig. 10A, 92; see [0072]; c.f. fig. 14A ) , wherein a top surface of the 1st source/drain region is at a level on or below a bottom surface of the uppermost inner spacer among the inner spacers ( see annotated fig. 14 above; the top surface of bottom source/drain region 1210 is at a level below a bottom surface of the uppermost inner spacer 64 (c.f. fig. 10A) among the indicated inner spacers ) . Regarding claim 15 , Xie discloses t he semiconductor device of claim 9, wherein the bottom surface of the 1st source/drain region ( fig. 14B, 1210; see [0077 ] ; note that the orientation of semiconductor structure 100 as shown in figs. 14A-B is flipped relative to page orientation such that backside regions (bottom, etc.) are shown above frontside (top, etc.) regions; also see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A ) is at a level below a top surface of the backside isolation structure ( fig. 14B, 12; see [0087] and c.f. fig. 14A; the bottom surface of bottom source/drain region 1210 is at a level below a top surface of the insulator layer 12 ) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 and 10 are rejected under 35 U.S.C. 103 as obvious over Xie in view of Lilak et al. ( US 20200294998 A1 ), hereinafter referred to as “ Lilak ”. Regarding claim 2 , Xie discloses the semiconductor device of claim 1 . Xie fails to disclose wherein an upper portion of the backside contact structure and the entire 1st source/drain region have an equal width in a channel length direction. Lilak discloses backside contact structures ( Lilak fig. 1A, 103; see Lilak [0013] ) for a stacked nanostructure transistor ( see Lilak fig. 1A; also see Lilak [0012]; see [0008] and note that the disclosed techniques of Lilak can be applied to nanosheet or gate-all-around transistors ), wherein an upper portion of a backside contact structure ( Lilak fig. 1A, 138; see specifically the backside source/drain contact 138 above interconnect 128 and below central source/drain region 124A; see Lilak [0028] and [0056] ; also see Lilak [0005] and note that figs. 3A-9D show various stages in the fabrication of the backside contact structures shown in fig. 1A ) and a 1st source/drain region ( Lilak fig. 1A, 124A; see specifically the central source/drain region 124A; see Lilak [0022]-[0024]) have an equal width in a channel length direction (see Lilak fig. 1A: the central backside source/drain contact 138 and the central source/drain region 124A have an equal width in a channel length direction defined by the length direction of nanowires 116A (i.e. the direction indicated by width W1)). The equal width teachings of Lilak are incorporated into the semiconductor device of Xie, wherein the combination discloses wherein an upper portion of the backside contact structure (Xie fig. 14A, 1300) and the 1st source/drain region (Xie fig. 14B, 1210 ; c.f. Xie fig. 14A ; see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A ) have an equal width in a channel length direction (see the equal width of 1 st source/drain region and backside contact structure as disclosed in Lilak fig. 1A) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Xie with the equal width teachings of Lilak to increase the amount of backside isolation material (Xie fig. 14B, 12; c.f. Xie fig. 14A) surrounding the 1 st source/drain region and backside contact structure (if the 1 st source/drain region and the backside contact structure have an equal width instead of the increasing divergent widths of both structures as shown in Xie fig. 14A, there would be more backside isolation material (i.e. insulator layer 12) surrounding said structures) and thereby better protect said structures from damage imparted by potential cracks in the backside isolation material. Regarding claim 10 , Xie discloses the semiconductor device of claim 9 . Xie fails to disclose wherein an upper portion of the backside contact structure and the entire 1st source/drain region have an equal width in a channel length direction. Lilak discloses backside contact structures ( Lilak fig. 1A, 103; see Lilak [0013]) for a stacked nanostructure transistor (see Lilak fig. 1A; also see Lilak [0012]; see [0008] and note that the disclosed techniques of Lilak can be applied to nanosheet or gate-all-around transistors), wherein an upper portion of a backside contact structure ( Lilak fig. 1A, 138; see specifically the backside source/drain contact 138 above interconnect 128 and below central source/drain region 124A; see Lilak [0028] and [0056]; also see Lilak [0005] and note that figs. 3A-9D show various stages in the fabrication of the backside contact structures shown in fig. 1A) and a 1st source/drain region ( Lilak fig. 1A, 124A; see specifically the central source/drain region 124A; see Lilak [0022]-[0024]) have an equal width in a channel length direction (see Lilak fig. 1A: the central backside source/drain contact 138 and the central source/drain region 124A have an equal width in a channel length direction defined by the length direction of nanowires 116A (i.e. the direction indicated by width W1)). The equal width teachings of Lilak are incorporated into the semiconductor device of Xie, wherein the combination discloses wherein an upper portion of the backside contact structure (Xie fig. 14A, 1300) and the 1st source/drain region (Xie fig. 14B, 1210 ; c.f. Xie fig. 14A; see [0086]: fig. 14B is a cross-sectional view of semiconductor structure 100 perpendicular to the channel-length view of fig. 14A ) have an equal width in a channel length direction (see the equal width of 1 st source/drain region and backside contact structure as disclosed in Lilak fig. 1A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Xie with the equal width teachings of Lilak to increase the amount of backside isolation material (Xie fig. 14B, 12; c.f. Xie fig. 14A) surrounding the 1 st source/drain region and backside contact structure (if the 1 st source/drain region and the backside contact structure have an equal width instead of the increasing divergent widths of both structures as shown in Xie fig. 14A, there would be more backside isolation material (i.e. insulator layer 12) surrounding said structures) and thereby better protect said structures from damage imparted by potential cracks in the backside isolation material. Claims 12-14 are rejected under 35 U.S.C. 103 as obvious over Xie in view of Mukesh et al. ( US 20240096951 A1 ) , hereinafter referred to as “ Mukesh” (note that Mukesh qualifies as prior art under 35 U.S.C. 102(a)(2)) Regarding claim 12 , Xie discloses the semiconductor device of claim 11 . Xie fails to disclose wherein the bottom surface of the 1st source/drain region is at a level on or above a bottom surface of the lowermost inner spacer among the inner spacers. Mukesh discloses a stacked FET device ( Mukesh fig. 22A-B, see Mukesh [0107]; also see Mukesh [0003] ) incorporating a backside power distribution network ( Mukesh fig. 22A, 84; see Mukesh [0106]; also see Mukesh [0049] and note that figs. 1-22B show the same semiconductor structure (part of the disclosed stacked FET device ) at various fabrication stages) , wherein the stacked FET comprises: a first source/drain region ( Mukesh fig. 22A, 28; see [0062] ) connected to a backside contact structure ( Mukesh fig. 22A, 80; see [0103] ) that is surrounded by a backside isolation structure ( Mukesh fig. 22A, 16; see [0059] -[ 0060] ); a first channel structure ( Mukesh fig. 22A, 20; see [0055] -[ 0056]; see [0050]: channel nanosheets 20 are connected to first source/drain region 28 ) that is surrounded by a gate structure ( Mukesh fig. 22A, 50B; see [0077] ) and connected to the first source/drain region; and a plurality of inner spacers ( Mukesh fig. 22A, 26; see [0061] ) formed between the first source/drain region and the gate structure in a channel length direction (the channel length direction being along the length of channel nanosheets 20 in Mukesh fig. 22A) , wherein the bottom surface of the 1st source/drain region is at a level on or above a bottom surface of the lowermost inner spacer among the inner spacers (see Mukesh fig. 22A: the bottom surface of first source/drain region 28 is on the level of the bottom surface of the lowermost inner spacer 26 (as indicated above)) . Note also that , in the stacked FET device of Mukesh, the bottom surface of the first source/drain region (Mukesh fig. 22A, 28) is on the level of both a bottom surface of the gate structure (Mukesh fig. 22A, 50B) and a top surface of the backside isolation structure (Mukesh fig. 22A , 16 ). The 1 st source/drain region of Mukesh is incorporated as the 1 st source/drain region of Xie, wherein the combination discloses wherein the bottom surface of the 1st source/drain region is at a level on or above a bottom surface of the lowermost inner spacer among the inner spacers . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Xie with the 1 st source/drain region of Mukesh to further isolate adjacent source/drain regions from each other ( since the 1 st source/drain region of Mukesh has less depth, the amount of isolation material between adjacent source/drain regions is increased ) and reduce the likelihood of a short circuit therebetween; and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the 1 st source/drain region of Xie ( Xie fig. 14A, 1210; c.f. fig. 14B ) with the 1 st source/drain region of Mukesh ( Mukesh fig. 22A, 28 ) to obtain predictable results ( source/drain regions in FET devices are well known in the art and their function as source/drain nodes for transistors is predictable ). Regarding claim 13 , Xie and Mukesh disclose t he semiconductor device of claim 9, wherein the bottom surface of the 1st source/drain region (Mukesh fig. 22A, 28; see Mukesh [0062]) is at a level on or above a bottom surface of the gate structure (Xie fig. 10A, 92; see Xie [0072]; c.f. fig. 14A; applicant is reminded of the flipped orientation of semiconductor structure 100 relative to the page; in the combined device, the bottom surface of the first source/drain region (from Mukesh) is at a level on a bottom surface of the gate structure ) . Regarding claim 14 , Xie and Mukesh disclose the semiconductor device of claim 9, wherein the bottom surface of the 1st source/drain region ( Mukesh fig. 22A, 28; see Mukesh [0062] ) is at a level on or above a top surface of the backside isolation structure ( Xie fig. 14B, 12; c.f. fig. 14A; applicant is reminded of the flipped orientation of semiconductor structure 100 relative to the page; in the combined device, the bottom surface of the first source/drain region (from Mukesh) is at a level on a top surface of the backside isolation structure (insulator layer 12 from Xie fig. 14A-B ; note that Mukesh also teaches this limitation in Mukesh fig. 22A wherein a bottom surface of first source/drain region ( 28 ) is at a level on a top surface of the backside isolation structure (16) ) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT HAMNER F COLLINS whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-5187 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F, 8am-5pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Steven Loke can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-1657 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAMNER FITZHUGH COLLINS IV/ Examiner, Art Unit 2818 /STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818