DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 20 and 24 are objected to because of the following informalities:
Claim 20 recites “the cooling solution and solution and” which should be replaced with “the cooling solution and”, to improve claim language.
Claim 24 recites “the at least digital device layers” which should be replaced with “the at least two digital device layers” for consistence with claim language.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/509,410 (hereinafter Aplication’410) in view of Li et al. (US 2015/0279431, hereinafter Li).
Claim 1 of Application’410 recites an integrated circuit (IC) die stack, comprising:
a digital device layer (line 2 of claim 1);
a cooling solution on a first side of the digital device layer (line 3 of claim 1); and
an underlying layer (e.g., a plurality of memory layers) (lines 5-6 of claim 1) on a second side of the digital device layer opposite the first side thereof.
Further, claim 1 of Application’410 does not recite the underlying layer having lower power consumption relative to digital device layer.
However, Li teaches an integrated circuit (IC) die stack comprising an underlying layer (e.g., memory die stack 105) (Li, Figs. 3, 6, ¶0020, ¶0024, ¶0035) on a second side (e.g., a bottom side) of the digital device layer (102b) opposite the first side thereof, wherein the underlying layer (105) having lower power consumption (e.g., heat produced by a logic die is greater than that of memory dies) (Li, Figs. 3, 6, ¶0021) relative to digital device layer (102b), and the digital device layer (102b) including logic die is placed over the memory dies (105) to reduce heat flow through the memory dies.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify claim 1 of Application’410 by forming an underlying layer including memory layers as taught by Li to have the IC die stack, wherein the underlying layer having lower power consumption relative to digital device layer, in order to provide improved memory stack with reduced heat flow through the memory dies (Li, ¶0001, ¶0021-¶0022, ¶0027).
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-8, 10, 19, 22, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2012/0146207 to Chou et al. (hereinafter Chou).
With respect to claim 1, Chou discloses an integrated circuit (IC) die stack (Chou, Fig. 3, ¶0003, ¶0013-¶0019, ¶0029-¶0039), comprising:
a digital device layer (e.g., functional chip 301 is a logic chip including a processor, see the annotated Fig. 3 of Chou below) (Chou, Fig. 3, ¶0029);
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a cooling solution (e.g., a heat sink H) (Chou, Fig. 3, ¶0035) on a first side (e.g., a top side) of the digital device layer (301); and
an underlying layer (e.g., memory chips 305/307) (Chou, Fig. 3, ¶0029) on a second side (e.g., a bottom side) of the digital device layer (301) opposite the first side thereof, the underlying layer (305/307) having lower power consumption (e.g., logic chip has a high operation temperature and a thermal design power (TDP) greater than 70W, but TDP of memory does not exceed 5W) (Chou, Fig. 3, ¶0014-¶0018) relative to digital device layer (301).
Regarding claim 2, Chou discloses the IC die stack according to claim 1. Further, Chou discloses the IC die stack, wherein the underlying layer (e.g., memory chips 305/307) (Chou, Fig. 3, ¶0029) is a plurality of memory layers that are electrically interconnected (e.g., with through silicon vias (TSVs) T1 and T2) (Chou, Fig. 3, ¶0037-¶0038) to the digital device layer (301) within the IC die stack.
Regarding claim 3, Chou discloses the IC die stack according to claim 2. Further, Chou discloses the IC die stack, wherein the digital device layer (301) and the plurality of memory layers (305/307) are electrically interconnected with through-silicon vias (TSVs) (T1/T2) (Chou, Fig. 3, ¶0037-¶0038).
Regarding claim 4, Chou discloses the IC die stack according to claim 3. Further, Chou discloses the IC die stack, wherein the TSVs (e.g., T1) are adapted for coupling to external connections (e.g., conductive bumps BP) (Chou, Fig. 3, ¶0035, ¶0037).
Regarding claim 7, Chou discloses the IC die stack according to claim 1. Further, Chou discloses the IC die stack, wherein the digital device layer (301) is a memory interface layer (e.g., including interface I1) (Chou, Fig. 3, ¶0031-¶0032, ¶0037).
Regarding claim 8, Chou discloses the IC die stack according to claim 1. Further, Chou discloses the IC die stack, wherein the digital device layer (301) (Chou, Fig. 3, ¶0029) is selected from the group consisting of a central processing unit (CPU) layer, a digital signal processor (DSP) layer, and a graphics processing unit (GPU) layer.
Regarding claim 10, Chou discloses the IC die stack according to claim 1. Further, Chou discloses the IC die stack, wherein the cooling solution is a thermal dissipation device with heat transfer enhancement structures selected from the group consisting of a heat sink (H) (Chou, Fig. 3, ¶0035), and a heat sink with fins.
With respect to claim 19, Chou discloses a memory stack (Chou, Fig. 3, ¶0003, ¶0013-¶0019, ¶0029-¶0039), comprising:
a plurality of memory layers (e.g., memory chips 305/307, see the annotated Fig. 3 of Chou above) (Chou, Fig. 3, ¶0029) stacked one on top of another;
at least two digital device layers (e.g., functional chip 301, a logic chip including a processor, and input/output chip 303) (Chou, Fig. 3, ¶0019, ¶0029) attached and electrically interconnected (e.g., with through silicon vias (TSVs) T1) (Chou, Fig. 3, ¶0037) to the plurality of memory layers (305/307); and
a cooling solution (e.g., a heat sink H) (Chou, Fig. 3, ¶0035) located at one end (e.g., a top end) of the memory stack of the plurality of memory layers (305/307) and the at least two digital device layers (301/303).
Regarding claim 22, Chou discloses the memory stack according to claim 19. Further, Chou discloses the memory stack, wherein at least one of the plurality of memory layers (305/307) (Chou, Fig. 3, ¶0029) is located between the at least two digital device layers (301 and 303).
Regarding claim 24, Chou discloses the memory stack according to claim 19. Further, Chou discloses the memory stack, wherein at least two digital device layers (301/303) (Chou, Fig. 3, ¶0029, ¶0031-¶0032) are selected from the group consisting of a memory interface layer, (e.g., device layers 301 and 303 include interface I1 and I2, respectively), a central processing unit (CPU) layer, a digital signal processor (DSP) layer, and a graphics processing unit (GPU) layer.
Claims 1-5, 8, 10, 19, 22, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0279431 to Li.
With respect to claim 1, Li discloses an integrated circuit (IC) die stack (Li, Figs. 3, 6, ¶0001, ¶0015-¶0036), comprising:
a digital device layer (e.g., logic die 102b, see the annotated Fig. 3 of Li below) (Li, Figs. 3, 6, ¶0024-¶0026, ¶0035);
a cooling solution (e.g., thermally conductive casing 110 to provide a heat spread) (Li, Figs. 3, 6, ¶0017) on a first side (e.g., a top side) of the digital device layer (102b); and
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an underlying layer (e.g., memory die stack 105) (Li, Figs. 3, 6, ¶0020, ¶0024, ¶0035) on a second side (e.g., a bottom side) of the digital device layer (102b) opposite the first side thereof, the underlying layer (105) having lower power consumption (e.g., heat produced by a logic die is greater than that of memory dies) (Li, Figs. 3, 6, ¶0021) relative to digital device layer (102b).
Regarding claim 2, Li discloses the IC die stack according to claim 1. Further, Li discloses the IC die stack, wherein the underlying layer (e.g., memory dies stack 105 including memory dies 103) (Li, Figs. 3, 6, ¶0020, ¶0024, ¶0035) is a plurality of memory layers (e.g., memory dies 103) that are electrically interconnected (e.g., with through stack interconnects 334) (Li, Figs. 3, 6, ¶0016, ¶0024) to the digital device layer (102b) within the IC die stack.
Regarding claim 3, Li discloses the IC die stack according to claim 2. Further, Li discloses the IC die stack, wherein the digital device layer (102b) and the plurality of memory layers (103) are electrically interconnected with through-silicon vias (TSVs) (334) (Li, Figs. 3, 6, ¶0024).
Regarding claim 4, Li discloses the IC die stack according to claim 3. Further, Li discloses the IC die stack, wherein the TSVs (e.g., 334) are adapted for coupling to external connections (e.g., interconnects 332) (Li, Figs. 3, 6, ¶0024, ¶0035).
Regarding claim 5, Li discloses the IC die stack according to claim 4. Further, Dokania discloses the IC die stack, wherein the external connections (e.g., interconnects 332) (Li, Fig. 4B, ¶0015, ¶0024, ¶0035) are adapted for coupling to an interposer substrate (122).
Regarding claim 8, Li discloses the IC die stack according to claim 1. Further, Li discloses the IC die stack, wherein the digital device layer (102b) (Li, Figs. 3-4, 6, ¶0020, ¶0029) is selected from the group consisting of a microcontroller.
Regarding claim 10, Li discloses the IC die stack according to claim 1. Further, Li discloses the IC die stack, wherein the cooling solution is a thermal dissipation device with heat transfer enhancement structures selected from the group consisting of a heat sink (e.g., thermally conductive casing 110 to provide a heat spread) (Li, Figs. 3, 6, ¶0017).
With respect to claim 19, Li discloses a memory stack (Li, Figs. 3-4, ¶0001, ¶0015-¶0029), comprising:
a plurality of memory layers (e.g., memory dies 103) (Li, Fig. 3, ¶0024) stacked one on top of another;
at least two digital device layers (e.g., logic dies 102a and 102b) (Li, Fig. 3, ¶0024-¶0026) attached and electrically interconnected (e.g., with through silicon vias (TSVs) 334) (Li, Fig. 3, ¶0024) to the plurality of memory layers (103); and
a cooling solution (e.g., thermally conductive casing 110 to provide a heat spread) (Li, Fig. 3, ¶0017) located at one end (e.g., a top end) of the memory stack of the plurality of memory layers (103) and the at least two digital device layers (102a/102b).
Regarding claim 22, Li discloses the memory stack according to claim 19. Further, Li discloses the memory stack, wherein at least one of the plurality of memory layers (103) (Li, Fig. 3, ¶0024-¶0026) is located between the at least two digital device layers (102a and 102b).
Regarding claim 24, Li discloses the memory stack according to claim 19. Further, Li discloses the memory stack, wherein the at least two digital device layers (102a/102b) (Li, Figs. 3-4, ¶0020, ¶0029) are selected from the group consisting of a microcontroller.
Claims 1-6, 8, 10, 19, 20, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0059491 to Dokania et al. (hereinafter Dokania) (the reference US 2015/0279431 by Li is presented as evidence).
With respect to claim 1, Dokania discloses an integrated circuit (IC) die stack (Dokania, Figs. 4A-4B, 5A-5B, ¶0002, ¶0078-¶0090, ¶0094-¶0095), comprising:
a digital device layer (e.g., a compute die 402 including a processor and/or application specific circuit (ASIC), see the annotated Fig. 4B of Dokania below) (Dokania, Fig. 4B, ¶0084, ¶0088);
a cooling solution (e.g., a heat sink 315) (Dokania, Fig. 4B, ¶0074, ¶0083) on a first side (e.g., a top side) of the digital device layer (402); and
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an underlying layer (e.g., memory dies 403) (Dokania, Fig. 4B, ¶0088) on a second side (e.g., a bottom side) of the digital device layer (402) opposite the first side thereof, the underlying layer (403) having lower power consumption (e.g., having compute die below the memory die causes thermal issue because the heat sink is away from the compute die (Dokania, ¶0034); it is known in the art that heat produced by a logic die is greater than that of memory dies, as evidenced by Li, ¶0021) relative to digital device layer (402).
Regarding claim 2, Dokania discloses the IC die stack according to claim 1. Further, Dokania discloses the IC die stack, wherein the underlying layer (e.g., memory dies 403) (Dokania, Fig. 4B, ¶0088) is a plurality of memory layers that are electrically interconnected (e.g., with through silicon vias (TSVs) 401c) (Dokania, Fig. 4B, ¶0089, ¶0082) to the digital device layer (402) within the IC die stack.
Regarding claim 3, Dokania discloses the IC die stack according to claim 2. Further, Dokania discloses the IC die stack, wherein the digital device layer (402) and the plurality of memory layers (403) are electrically interconnected with through-silicon vias (TSVs) (401c) (Dokania, Fig. 4B, ¶0089, ¶0082).
Regarding claim 4, Dokania discloses the IC die stack according to claim 3. Further, Dokania discloses the IC die stack, wherein the TSVs (401c) are adapted for coupling to external connections (e.g., C4 bumps) (Dokania, Fig. 4B, ¶0089, ¶0090).
Regarding claim 5, Dokania discloses the IC die stack according to claim 4. Further, Dokania discloses the IC die stack, wherein the external connections (C4 bumps) (Dokania, Fig. 4B, ¶0089, ¶0087) are adapted for coupling to an interposer substrate (e.g., 302 in Fig. 4B).
Regarding claim 6, Dokania discloses the IC die stack according to claim 5. Further, Dokania discloses the IC die stack, further comprising a system on a chip (SoC) (Dokania, Figs. 4B, 5A, ¶0089-¶0090, ¶0094) attached to the interposer substrate (e.g., 302 in Fig. 5A) and adapted for coupling through the external connections and TSVs to the digital device layer (e.g., computer die 402 over memory according to the embodiment of Fig. 4B) and plurality of memory layers (403 in Fig. 4B).
Regarding claim 8, Dokania discloses the IC die stack according to claim 1. Further, Dokania discloses the IC die stack, wherein the digital device layer (402) (Dokania, Fig. 4B, ¶0084, ¶0088) is selected from the group consisting of an application specific integrated circuit (ASIC) layer.
Regarding claim 10, Dokania discloses the IC die stack according to claim 1. Further, Dokania discloses the IC die stack, wherein the cooling solution is a thermal dissipation device with heat transfer enhancement structures selected from the group consisting of a heat sink 315) (Dokania, Fig. 4B, ¶0074, ¶0083), and a heat sink with fins.
With respect to claim 19, Dokania discloses a memory stack (Dokania, Figs. 4A-4B, 5A-5B, ¶0002, ¶0078-¶0090, ¶0094-¶0095), comprising:
a plurality of memory layers (e.g., memory dies 403) (Dokania, Fig. 4B, ¶0088) stacked one on top of another;
at least two digital device layers (e.g., a compute die 402 including a processor and/or application specific circuit (ASIC) and a controller logic die 401) (Dokania, Fig. 4B, ¶0084, ¶0088) attached and electrically interconnected (e.g., with through silicon vias (TSVs) 401c) (Dokania, Fig. 4B, ¶0089, ¶0082) to the plurality of memory layers (403); and
a cooling solution (e.g., a heat sink 315) (Dokania, Fig. 4B, ¶0074, ¶0083) located at one end (e.g., a top end) of the memory stack of the plurality of memory layers (403) and the at least two digital device layers (401/402).
Regarding claim 20, Dokania discloses the memory stack according to claim 19. Further, Dokania discloses the memory stack, wherein the at least two digital device layers (401 and 402) (Dokania, Fig. 4B, ¶0089) are located between the cooling solution (315) and any one or more of the plurality of memory layers (403).
Regarding claim 24, Dokania discloses the memory stack according to claim 19. Further, Dokania discloses the memory stack, wherein the at least two digital device layers (401/402) (Dokania, Fig. 4B, ¶0084, ¶0088) are selected from the group consisting of an application specific integrated circuit (ASIC).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0146207 to Chou in view of Dokania (US 2023/0059491).
Regarding claim 5, Chou discloses the IC die stack according to claim 4. Further, Chou discloses the IC die stack, wherein the external connections (BP) are adapted for coupling to a package substrate (Sub) (Chou, Fig. 3, ¶0035, ¶0037), but does not specifically disclose an interposer substrate.
However, Dokania teaches forming the IC die stack, wherein the external connections (C4 bumps) (Dokania, Figs. 4B, 5A, ¶0089, ¶0094) are adapted for coupling to an interposer substrate (e.g., 302 in Figs. 4B and 5A), to provide an artificial intelligence system (AI) including die assembly having computational block over memory dies to reduce power consumption.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the IC die stack of Chou by forming the package substrate as an interposer of Dokania to have the IC die stack, wherein the external connections are adapted for coupling to an interposer substrate, in order to provide an artificial intelligence system (AI) including die assembly having computational block over memory dies to reduce power consumption (Dokania, ¶0089, ¶0087).
Regarding claim 6, Chou in view of Dokania discloses the IC die stack according to claim 5. Further, Chou does not specifically disclose the IC die stack, further comprising a system on a chip (SoC) attached to the interposer substrate and adapted for coupling through the external connections and TSVs to the digital device layer and plurality of memory layers.
However, Dokania teaches forming the IC die stack, further comprising a system on a chip (SoC) (Dokania, Figs. 4B, 5A, ¶0089-¶0090, ¶0094) attached to the interposer substrate (e.g., 302 in Fig. 5A) and adapted for coupling through the external connections and TSVs to the digital device layer (e.g., computer die 402 over memory according to the embodiment of Fig. 4B) and plurality of memory layers (403 in Fig. 4B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the IC die stack of Chou/Dokania by forming a system on a chip (SoC) on an interposer as taught by Dokania to have the IC die stack, further comprising a system on a chip (SoC) attached to the interposer substrate and adapted for coupling through the external connections and TSVs to the digital device layer and plurality of memory layers, in order to provide an artificial intelligence system (AI) including die assembly having computational block over memory dies to reduce power consumption (Dokania, ¶0089, ¶0087).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0059491 to Dokania in view of Watanabe et al. (US 2014/0040532, hereinafter Watanabe).
Regarding claim 7, Dokania discloses the IC die stack according to claim 1. Further, Dokania does not specifically disclose the IC die stack, wherein the digital device layer is a memory interface layer.
However, Watanabe teaches a logic device layer (122) (Watanabe, Fig. 1, ¶0024) implementing logic to facilitate access to the memory of the stacked memory device (102) and including a memory interface (130).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the IC die stack of Dokania by forming a device layer of Dokania as a logic device layer including a memory interface as taught by Watanabe to have the IC die stack, wherein the digital device layer is a memory interface layer, in order to facilitate access to the memory of the stacked memory device (Watanabe, ¶0024).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0146207 to Chou in view of Pappu (US 2018/0096735).
Regarding claim 9, Chou discloses the IC die stack according to claim 1. Further, Chou discloses the IC die stack, wherein the underlying layer (memory layer 305/307) (Chou, Fig. 3, ¶0029, ¶0035) comprises a plurality of memory layers (305/307) including the first memory layer (307), and wherein the first memory layer (307) is farthest from the cooling solution (e.g., heat sink H) and electrically coupled to the digital device layer (301), but does not specifically disclose the IC die stack, further comprising a system on a chip (SoC) attached to a first memory layer of the underlying layer.
However, Chou teaches a logic chip (303) (Chou, Fig. 3, ¶0029-¶0033, ¶0037-¶0038) having an interface (I2) attached to a first memory layer (307) of the underlying layer (305/307), wherein the 3D chip is configured as a system on a chip (SoC), to provide improved stacked structure for a 3D chip with improved heat dissipation while maintaining the integrity of the memory chip (Chou, ¶0018-¶0020).
Further, Pappu teaches a memory stack, wherein a system on a chip (SoC) (105) (Pappu, Fig. 1B, ¶0067-¶0076) is attached to a first memory layer (110) of the memory layer stack (110/1115/120/125), to provide improved memory module having low power consumption and high bandwidth requirements.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the IC die stack of Chou by forming a stacked structure including a logic chip configured as a system on a chip (SoC) at the bottom of the memory stack as taught by Pappu to have the IC die stack, further comprising a system on a chip (SoC) attached to a first memory layer of the underlying layer, in order to provide improved memory module having low power consumption and high bandwidth requirements (Pappu, ¶0003, ¶0067-¶0068).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0059491 to Dokania in view of Pappu (US 2018/0096735).
Regarding claim 9, Dokania discloses the IC die stack according to claim 1. Further, Dokania discloses the IC die stack, wherein the underlying layer (memory layers 403) (Dokania, Fig. 4B, ¶0088) comprises a plurality of memory layers including the first memory layer (403N), and wherein the first memory layer (403N) is farthest from the cooling solution (e.g., heat sink 315) and electrically coupled to the digital device layer (401), but does not specifically disclose the IC die stack, further comprising a system on a chip (SoC) attached to a first memory layer of the underlying layer.
However, Pappu teaches a memory stack, wherein a system on a chip (SoC) (105) (Pappu, Fig. 1B, ¶0067-¶0076) is attached to a first memory layer (110) of the memory layer stack (110/1115/120/125), to provide improved memory module having low power consumption and high bandwidth requirements.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the IC die stack of Dokania by forming a stacked structure including a logic chip configured as a system on a chip (SoC) at the bottom of the memory stack as taught by Pappu to have the IC die stack, further comprising a system on a chip (SoC) attached to a first memory layer of the underlying layer, in order to provide improved memory module having low power consumption and high bandwidth requirements (Pappu, ¶0003, ¶0067-¶0068).
Claims 11-16, 18, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0059491 to Dokania in view of Bertin et al. (US Patent No. 5,561,622, hereinafter Bertin).
With respect to claim 11, Dokania discloses a memory stack (Dokania, Figs. 4A-4B, 5A-5B, ¶0002, ¶0078-¶0090, ¶0094-¶0095), comprising:
a plurality of memory layers (e.g., memory dies 403, see the annotated Fig. 4B of Dokania above) (Dokania, Fig. 4B, ¶0088) stacked one on top of another;
a cooling solution (e.g., a heat sink 315) (Dokania, Fig. 4B, ¶0074, ¶0083) located at one end (e.g., a top end) of the memory stack of the plurality of memory layers (403); and
a digital device layer (e.g., a compute die 402 including a processor and/or application specific circuit (ASIC) and a controller logic die 401) (Dokania, Fig. 4B, ¶0084, ¶0088).
Further, Dokania does not specifically disclose a digital device layer located between two of the plurality of memory layers.
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However, Bertin teaches forming a memory stack structure (Bertin, Figs. 5-6, Col. 1, lines 5-13; Col. 2, lines 3-24; Col. 4, lines 44-67; Col. 5, lines 1-6; Col. 7, lines 18-35) comprising a controlling logic layer, wherein the controlling logic layer (114’) of middle subassembly (110, see the annotated Fig. 6 of Bertin below) (Bertin, Fig. 6, Col. 7, lines 18-35) is located between two of the plurality of memory layers (114) of the upper and lower subassemblies (110), and electrically connected to each of the memory chip of the memory stack, to provide high density memory package integrated with controlling logic to obtain a powerful memory architecture having a function of a single higher level memory chip for next generation packaging with reduced dimensions.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the memory stack of Dokania by forming the memory stack structure including a plurality of memory subassemblies each having a logic chip as a device layer as taught by Bertin to have the memory stack, wherein a digital device layer located between two of the plurality of memory layers, in order to provide high density memory package integrated with controlling logic to obtain a powerful memory architecture having a function of a single higher level memory chip for next generation packaging with reduced dimensions (Bertin, Col. 1, lines 5-13; Col. 2, lines 3-24; Col. 4, lines 44-67; Col. 5, lines 1-6; Col. 7, lines 18-35).
Regarding claim 12, Dokania in view of Bertrin discloses the memory stack according to claim 11. Further, Dokania discloses the memory stack, wherein the digital device layer (401/402) and the plurality of memory layers (e.g., memory dies 403) (Dokania, Fig. 4B, ¶0088) are electrically interconnected (e.g., with through silicon vias (TSVs) 401c) (Dokania, Fig. 4B, ¶0089, ¶0082).
Regarding claim 13, Dokania in view of Bertrin discloses the memory stack according to claim 12. Further, Dokania discloses the memory stack, wherein the digital device layer (402) and the plurality of memory layers (403) are electrically interconnected with through-silicon vias (TSVs) (401c) (Dokania, Fig. 4B, ¶0089, ¶0082).
Regarding claim 14, Dokania in view of Bertrin discloses the memory stack according to claim 13. Further, Dokania discloses the memory stack, wherein the TSVs (401c) are adapted for coupling to external connections (e.g., C4 bumps) (Dokania, Fig. 4B, ¶0089, ¶0090).
Regarding claim 15, Dokania in view of Bertrin discloses the memory stack according to claim 14. Further, Dokania discloses the memory stack, wherein the external connections (C4 bumps) (Dokania, Fig. 4B, ¶0089, ¶0087) are adapted for coupling to an interposer substrate (e.g., 302 in Fig. 4B).
Regarding claim 16, Dokania in view of Bertrin discloses the memory stack according to claim 15. Further, Dokania discloses the memory stack, further comprising a system on a chip (SoC) (Dokania, Figs. 4B, 5A, ¶0089-¶0090, ¶0094) attached to the interposer substrate (e.g., 302 in Fig. 5A) and adapted for coupling through the external connections and TSVs to the digital device layer (e.g., computer die 402 over memory according to the embodiment of Fig. 4B).
Regarding claim 18, Dokania in view of Bertrin discloses the memory stack according to claim 11. Further, Dokania discloses the memory stack, wherein the digital device layer (402) (Dokania, Fig. 4B, ¶0084, ¶0088) is selected from the group consisting of an application specific integrated circuit (ASIC) layer.
Regarding claims 21-23, Dokania discloses the memory stack according to claim 19. Further, Dokania does not specifically disclose the memory stack, wherein the plurality of memory layers are located between the cooling solution and the at least two digital device layers (as claimed in claim 21); wherein at least one of the plurality of memory layers is located between the at least two digital device layers (as claimed in claim 22); wherein at least one of the plurality of memory layers is located between the cooling solution and the at least two digital device layers (as claimed in claim 23).
However, Bertin teaches forming a memory stack structure (Bertin, Figs. 5-6, Col. 1, lines 5-13; Col. 2, lines 3-24; Col. 4, lines 44-67; Col. 5, lines 1-6; Col. 7, lines 18-35) comprising a controlling logic layer, wherein the controlling logic layer (114’) of middle subassembly (110) (Bertin, Fig. 6, Col. 7, lines 18-35) is located between two of the plurality of memory layers (114) of the upper and lower subassemblies (110), and wherein the plurality of memory layers (114) of upper subassembly (110) are located between the top layer (118) of the stack and the at least two digital device layers (logic layers 114’) of the middle and lower subassemblies (110); wherein at least one of the plurality of memory layers (114, of the middle subassembly 110) is located between the at least two digital device layers (114’) of the middle and lower subassemblies (110); wherein at least one of the plurality of memory layers (114, of the upper subassembly 110) is located between the top layer of the stack and the at least two digital device layers (114’) of the middle and lower subassemblies (110), to provide high density memory package integrated with controlling logic to obtain a powerful memory architecture having a function of a single higher level memory chip for next generation packaging with reduced dimensions.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the memory stack of Dokania by forming the memory stack structure including a plurality of memory subassemblies each having a logic chip as a device layer as taught by Bertin to have the memory stack, wherein the plurality of memory layers are located between the cooling solution and the at least two digital device layers (as claimed in claim 21); wherein at least one of the plurality of memory layers is located between the at least two digital device layers (as claimed in claim 22); wherein at least one of the plurality of memory layers is located between the cooling solution and the at least two digital device layers (as claimed in claim 23), in order to provide high density memory package integrated with controlling logic to obtain a powerful memory architecture having a function of a single higher level memory chip for next generation packaging with reduced dimensions (Bertin, Col. 1, lines 5-13; Col. 2, lines 3-24; Col. 4, lines 44-67; Col. 5, lines 1-6; Col. 7, lines 18-35).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0059491 to Dokania in view of Bertin (US Patent No. 5,561,622) as applied to claim 11, and further in view of Watanabe (US 2014/0040532).
Regarding claim 17, Dokania in view of Bertin discloses the memory stack according to claim 11. Further, Dokania does not specifically disclose the memory stack, wherein the digital device layer is a memory interface layer.
However, Watanabe teaches a logic device layer (122) (Watanabe, Fig. 1, ¶0024) implementing logic to facilitate access to the memory of the stacked memory device (102) and including a memory interface (130).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the memory stack of Dokania/Bertin by forming a device layer of Dokania/Bertin as a logic device layer including a memory interface as taught by Watanabe to have the memory stack, wherein the digital device layer is a memory interface layer, in order to facilitate access to the memory of the stacked memory device (Watanabe, ¶0024).
Claims 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0352463 to Jeng et al. (hereinafter Jeng) in view of Dokania (US 2023/0059491).
With respect to claim 25, Jeng discloses an electronic system (Jeng, Figs. 2, 12, ¶0002, ¶0012, ¶0014-¶0016, ¶0027-¶0028), comprising:
at least one memory stack (e.g., memory dies or memory packages 52, see the annotated Fig. 2 of Jeng below) (Jeng, Fig. 2, ¶0027), each comprising
a plurality of memory layers; and
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a system on a chip (SoC) (50) (Jeng, Fig. 2, ¶0027) electrically coupled (e.g., with conductive path and through vias 42/46) (Jeng, Figs. 2, 12, ¶0024, ¶0028) to the at least one memory stack (52).
Further, Jeng does not specifically disclose that at least one memory stack, each comprising a digital device layer, a cooling solution on a first side of the digital device layer, and a plurality of memory layers on a second side of the digital device layer opposite to the first side thereof.
However, Dokania teaches forming a memory stack (Dokania, Figs. 4A-4B, 5A-5B, ¶0002, ¶0078-¶0090, ¶0094-¶0095), comprising: a plurality of memory layers (e.g., memory dies 403, see the annotated Fig. 4B of Dokania above) (Dokania, Fig. 4B, ¶0088) stacked one on top of another; a digital device layer (e.g., a compute die 402 including a processor and/or application specific circuit (ASIC)) (Dokania, Fig. 4B, ¶0084, ¶0088); a cooling solution (e.g., a heat sink 315) (Dokania, Fig. 4B, ¶0074, ¶0083) on a first side (e.g., a top side) of the digital device layer (402); and the plurality of memory layers (103) on a second side of the digital device layer (402) opposite to the first side thereof, to provide an artificial intelligence system (AI) including die assembly having computational block over memory dies to reduce power consumption.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the electronic system of Jeng by forming the memory stack including a compute die as taught by Dokania to have the electronic system, wherein at least one memory stack, each comprising a digital device layer, a cooling solution on a first side of the digital device layer, and a plurality of memory layers on a second side of the digital device layer opposite to the first side thereof, in order to provide an artificial intelligence system (AI) including die assembly having computational block over memory dies to reduce power consumption (Dokania, ¶0089, ¶0087).
Regarding claim 26, Jeng in view of Dokania discloses the electronic system according to claim 25. Further, Jeng does not specifically disclose that the digital device layer is selected from the group consisting of a memory interface layer, a microcontroller layer, a microprocessor layer, a mixed signal processor layer, a central processing unit (CPU) layer, a programmable logic array (PLA) layer, an application specific integrated circuit (ASIC) layer, a digital signal processor (DSP) layer, a graphics processing unit (GPU) layer, a field programmable gate array (FPGA) layer, a neural processing unit layer, and a tensor processing unit layer.
However, Dokania teaches forming a memory stack, wherein the digital device layer (402) (Dokania, Fig. 4B, ¶0084, ¶0088) is selected from the group consisting of an application specific integrated circuit (ASIC) layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the electronic system of Jeng/Dokania by forming the memory stack including a compute die as taught by Dokania to have the electronic system, wherein the digital device layer is selected from the group consisting of an application specific integrated circuit (ASIC) layer, in order to provide an artificial intelligence system (AI) including die assembly having computational block over memory dies to reduce power consumption (Dokania, ¶0089, ¶0087).
Regarding claim 27, Jeng in view of Dokania discloses the electronic system according to claim 25. Further, Jeng discloses the electronic system, further comprising: an interposer substrate (20) (Jeng, Fig. 2, ¶0014-¶0016, ¶0024, ¶0027) attached to the at least one memory stack (52); and the SoC (50) attached to the interposer substrate (20) and electrically coupled (e.g., with conductive path and through vias 42/46) (Jeng, Figs. 2, 12, ¶0024, ¶0028) to the at least one memory stack (20) through the interposer substrate (20).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891