Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-10 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 11515249 to Huang et al. (Huang) in view of U.S. Pat. No. 9054095 to Pagaila.
Regarding Claim 1, Huang teaches in Fig. 2A at least, semiconductor package, comprising:
a first substrate 3’ including a first insulating layer 31 and a first wiring layer (first portion of inner via 33 directly disposed on interconnection via 39) disposed on or in the first insulating layer;
a first package 2’ disposed on the first substrate, and including a second substrate 12’, a first semiconductor chip disposed on the second substrate 4, first connection members 28 connecting the second substrate to the first semiconductor chip;
a second package 2 disposed on the first substrate, and including a third substrate 12, a second semiconductor chip disposed on the third substrate, second connection members connecting the third substrate to the second semiconductor chip (although not shown Huang teaches in 8:14-18 that the second package 2 may not be used for external connection, therefore explicitly envisioning embodiments where external connections to ICs 4 are connected; and at the very least motivating the person of ordinary skill to increase integration by adding additional functionality through circuitry);
1-1 connection members (33 on the left) connecting the first substrate to the first package; and
2-1 connection members (33 on the right) connecting the first substrate to the second package,
wherein the number of first connection members is greater than the number of 1-1 connection members (in duplicating the arrangement on the right and including a second IC 4, there would be four vs three), and
wherein the number of second connection members is greater than the number of 2-1 connection members (four vs. three).
Huang does not explicitly teach a first SERDES chip embedded in the second substrate a second SERDES chip embedded in the third substrate.
However, in analogous art, Pagaila teaches in Fig. 7 at least an IC 124 embedded in a package 210, analogous to the second or third packages of the claim, having another IC 152, analogous to the first or second semiconductor chip of the claim on top. It would have been obvious to the person of ordinary skill in the art before the time of filing to modify the package system of Huang with the packages of Pagaila in order to increase integration into a smaller footprint, which is a constant driving force in semiconductor packaging design. The IC 124 is broadly described and can essentially be any integrated circuit desired, including signal processing, which SERDES falls into. The person of ordinary skill having the benefit of Huang and Pagaila can readily arrange a design to fit application specific needs.
Regarding Claim 2, Huang and Pagaila teach the semiconductor package of Claim 1
wherein the second substrate 2’ includes a second insulating layer 20’, and second wiring layers 25’ disposed on or in the second insulating layer, and
wherein a pitch of one of the second wiring layers connected to the first connection members is smaller than a pitch of another of the second wiring layers connected to the 1-1 connection members (see Fig. 2A).
Regarding Claim 3, Huang and Pagaila teach the semiconductor package of Claim 2 wherein the third substrate includes a third insulating layer, and third wiring layers disposed on or in the third insulating layer, and wherein a pitch of one of the third wiring layers connected to the second connection members is smaller than a pitch of another of the third wiring layers connected to the 2-1 connection members (the duplicated package 2’ would be identical).
Regarding Claim 6, Huang and Pagaila teach the semiconductor package of claim 1,
wherein the first SERDES chip includes a serializer chip, and wherein the second SERDES chip includes a deserializer chip (all SERDES have a serializer and deserializer by definition, and the person of ordinary skill may apply any kind of functionality to the end product as taught by Pagaila above).
Regarding Claim 7, Huang and Pagaila teach the semiconductor package of Claim 6,
wherein the serializer chip includes first connection pads,
wherein the deserializer chip includes second connection pads,
wherein, in the first connection pads, the number of input connection pads is greater than the number of output connection pads, and
wherein, in the second connection pads, the number of output connection pads is greater than the number of input connection pads (limitations describe the functions of SER/DES, by definition a serializer has greater inputs than outputs as the data stream has been serialized, and vice versa).
Regarding Claim 8, Huang and Pagaila teach the semiconductor package of claim 1,
wherein the second substrate includes a second insulating layer, a second wiring layer disposed on or in the second insulating layer, and a first cavity penetrating through at least a portion of the second insulating layer, and wherein the first SERDES chip is disposed in the first cavity and is embedded by the second insulating layer (in the combination of Huang and Pagaila, Huang shows multiple second insulating layers 20’ any of which may be considered a second insulating layer having wiring layers 25’ thereon; and the IC 124 of Pagaila would be embedded in one of them, analogous to insulation layer 140 of Pagaila).
Regarding Claim 9, Huang and Pagaila teach the semiconductor package of claim 8,
wherein the third substrate includes a third insulating layer, and a third wiring layer disposed on or in the third insulating layer and a second cavity penetrating through at least a portion of the third insulating layer, and wherein the second SERDES chip is disposed in the second cavity and is embedded by the third insulating layer (the combined structure of Huang and Pagaila would be identically constructed on the left).
Regarding Claim 10, Huang and Pagaila teach the semiconductor package of claim 9,
wherein the second substrate further includes a first adhesive member interposed between the first SERDES chip and a bottom surface of the first cavity, and wherein the third substrate further includes a second adhesive member interposed between the second SERDES chip and a bottom surface of the second cavity (Pagaila shows an adhesive 214).
Regarding Claim 15, Huang and Pagaila teach a semiconductor package, comprising:
a first substrate comprising a first insulating layer and a first wiring layer disposed on or in the first insulating layer;
a first package disposed on the first substrate, and including a second substrate, a first semiconductor chip disposed on the second substrate, a first connection member connecting the second substrate to the first semiconductor chip, and a first SERDES chip embedded in the second substrate;
a second package disposed on the first substrate, and including a third substrate, a second semiconductor chip disposed on the third substrate, a second connection member connecting the third substrate to the second semiconductor chip, and a second SERDES chip embedded in the third substrate;
a 1-1 connection member connecting the first substrate to the first package; and
a 2-1 connection member connecting the first substrate to the second package (see above rejection of Claim 1),
wherein the first semiconductor chip and the second semiconductor chip are connected to each other by a path passing through the first SERDES chip, the second substrate, the first substrate, the third substrate, and the second SERDES chip (the person of ordinary skill having the benefit of Huang and Pagaila can readily arrange an IC package system to route signals as desired; this is a routine practice for engineers in the semiconductor industry).
Regarding Claim 16, Huang and Pagaila teach the semiconductor package of claim 15,
wherein the first SERDES chip includes a serializer chip, and
wherein the second SERDES chip includes a deserializer chip (definition of SERDES devices; each have a serializer and deserializer).
Regarding Claim 17, Huang and Pagaila teach the semiconductor package of claim 16,
wherein the serializer chip includes a circuit configured to convert a parallel signal into a serial signal, and
wherein the deserializer chip includes a circuit configured to convert a serial signal into a parallel signal (definition of SERDES functionality).
Regarding Claim 18, Huang and Pagaila teach the semiconductor package of claim 17,
wherein the number of signal paths output through the serializer chip is less than the number of signal paths output from the first semiconductor chip, and
wherein the number of signal paths input to the deserializer chip is less than the number of signal paths input to the second semiconductor chip (definition of SERDES functionality).
Regarding Claim 19, Huang and Pagaila teach the semiconductor package of claim 15,
wherein the second substrate includes a second insulating layer, a second wiring layer disposed on or in the second insulating layer, and a first cavity penetrating through at least a portion of the second insulating layer, and wherein the first SERDES chip is disposed in the first cavity and is embedded by the second insulating layer (see above rejection of Claim 8).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Huang and Pagaila as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. 20130049217 to Gong et al. (Gong).
Regarding Claim 13, Huang and Pagaila teach the semiconductor package of claim 1,
wherein the second substrate includes a second insulating layer, and a second wiring layer disposed on or in the second insulating layer,
wherein the third substrate includes a third insulating layer, and a third wiring layer disposed on or in the third insulating layer (multiple insulating layers 20, each with wiring 25 disposed thereon), but do not explicitly teach that the second insulating layer and the third insulating layer include an organic material.
However, in analogous art, Gong teaches in [0039] that dielectrics (as taught by Huang) and organic layers are interchangeably suitable for insulating layers in a laminated IC package, see MPEP 2144.06.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huang and Pagaila as applied to claim 1 above, and further in view of U.S. Pat. No. 10332854 to Katkar et al. (Katkar).
Regarding Claim 14, Huang and Pagaila teach the semiconductor package of claim 1, but do not explicitly teach that the first substrate, the second substrate and the third substrate are disposed be spaced apart from each other.
However, in analogous art, Katkar teaches in Fig. 1A at least, a stacked arrangement of IC packages that are spaced apart. It would have been obvious to the person of ordinary skill in the art before the time of filing to modify Huang and Pagaila with the teaching of Katkar to reduce thermal strain between the packages, as taught by Katkar throughout.
Allowable Subject Matter
Claims 4, 5, 11, 12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 4, Huang and Pagaila teach the semiconductor package of Claim 1
wherein the first substrate further includes a 1-1 insulating layer disposed on an uppermost side of the first insulating layer, but do not teach that a dissipation factor of the 1-1 insulating layer is smaller than a dissipation factor of the first insulating layer.
Regarding Claim 11, Huang and Pagaila teach the semiconductor package of Claim 1
wherein the second substrate includes a first core layer, a second insulating layer disposed on or below the first core layer, a second wiring layer disposed on or in the first core layer or the second insulating layer, but do not teach a first cavity penetrating through at least a portion of the first core layer, wherein the first SERDES chip is disposed in the first cavity, and wherein the first core layer includes a material different from the second insulating layer.
Regarding Claim 20, Huang and Pagaila teach the semiconductor package of Claim 1
wherein the second substrate includes a first core layer, a second insulating layer disposed on or below the first core layer, a second wiring layer disposed on or in the first core layer or the second insulating layer, but do not teach a first cavity penetrating through at least a portion of the first core layer, wherein the first SERDES chip is disposed in the first cavity, and wherein the first core layer includes a material different from the second insulating layer.
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812