Prosecution Insights
Last updated: May 29, 2026
Application No. 18/379,731

SEMICONDUCTOR DEVICE

Non-Final OA §102§103§112
Filed
Oct 13, 2023
Priority
Oct 20, 2022 — RE 10-2022-0135790
Examiner
ARMAND, MARC ANTHONY
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
878 granted / 1054 resolved
+15.3% vs TC avg
Minimal +4% lift
Without
With
+3.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
15 currently pending
Career history
1077
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
81.2%
+41.2% vs TC avg
§102
6.4%
-33.6% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1054 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation: “an entirety of the second active pattern overlaps the first active pattern,” is not clear because the first and second active pattern are separated by a second element separation structure. Therefore, the second active pattern will not be able to overlap the first active pattern. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of claim 15, reciting: “an entirety of the second active pattern overlaps the first active pattern,” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5,10-14 is/are rejected under 35 U.S.C. 102(a1) as being anticipated over Lee et al., (Lee) US 2021/0167059. Regarding claim 1, Lee shows in FIG. 2-20, and discloses a semiconductor device, comprising: a first element separation structure (SR)[0034](FIG.2), a second element separation structure (second SR), and a third element separation structure (Multiple SR) sequentially spaced apart (FIG. 20 also shows multiple SRs and separation 114)[0098] from each other in a first direction, the first element separation structure (SR), the second element separation structure (SR), and the third element separation structure (SR) extending in a second direction intersecting the first direction (FIG. 2-10); a first active pattern (CR region, first rectangle shown in FIG. 2, also EDR shown in FIG. 20) extending in the first direction between the first element separation structure and the second element separation structure (SRs); a second active pattern (second adjacent rectangle shown in FIG. 1, other EDR region in FIG. 20) extending in the first direction between the second element separation structure and the third element separation structure (SR), the second active pattern being separated from the first active pattern by the second element separation structure (SR), and a width of the first active pattern (EDR, first rectangle) in the second direction being greater than a width of the second active pattern in the second direction [0075](in FIG. 20, FA section of the first EDR is shown to be wider than FA of the second active region); a first gate electrode (GL) extending in the second direction on the first active pattern; and second gate electrodes (other GL)(shown in FIG. 7-10) extending in the second direction on the second active pattern. Regarding claim 2, Lee shows in FIG. 2-20, a semiconductor device, wherein: the first active pattern (CR rectangle in FIG. 2, FA section in FIG. 20) includes a first sidewall and a second sidewall opposite to each other in the second direction (on opposite sides of the rectangle), the second active (adjacent rectangular CR) pattern includes a third sidewall and a fourth sidewall opposite to each other in the second direction (on both sides of second CR box), and the first sidewall is on a same plane as the third sidewall (FIG. 2). Regarding claim 3, Lee shows in FIG. 2-20, a semiconductor device, wherein: the first active pattern (CR rectangle in FIG. 2, FA section in FIG. 20) includes a first sidewall and a second sidewall opposite to each other in the second direction, the second active pattern (other CR rectangle) includes a third sidewall and a fourth sidewall opposite to each other in the second direction, and in a plan view, the first sidewall and the third sidewall are spaced apart (spaced by SR) from each other by a first width in the second direction, and the second sidewall and the fourth sidewall are spaced apart (by other SR) from each other by a second width different from the first width in the second direction. Regarding claim 4, Lee shows in FIG. 2-20, a semiconductor device wherein: the first active pattern (CR rectangle in FIG. 2, FA section in FIG. 20) includes a first sidewall and a second sidewall opposite to each other in the second direction, the second active pattern (other CR rectangle) includes a third sidewall and a fourth sidewall opposite to each other in the second direction, and in a plan view, the first sidewall and the third sidewall are spaced apart (By SR) from each other by a first width in the second direction, and the second sidewall and the fourth sidewall are spaced apart (by SR) from each other by the first width in the second direction. Regarding claim 5, Lee shows in FIG. 2-20, a semiconductor device, wherein; the width of the first active pattern (CR rectangle in FIG. 2, FA section in FIG. 20) in the second direction is constant as a distance from the second element separation structure (SR) increases, and the width of the second active pattern (second CR rectangle) in the second direction is constant as a distance from the second element separation structure (SR) increases. Regarding claim 10, Lee shows in FIG. 2-20, a semiconductor device, wherein: the first active pattern (CR rectangle in FIG. 2, FA section in FIG. 20) includes a first lower pattern extending in the first direction (portion of FA), and a plurality of first sheet patterns (NSS)(see FIG. 20) spaced apart from the first lower pattern, the second active pattern (second rectangular and EDR section) includes a second lower pattern extending in the first direction, and a plurality of second sheet patterns (152) spaced apart from the second lower pattern (see FIG. 20), the first gate electrode (152M) surrounds the first sheet pattern, the second gate electrodes (other 152M) surround the plurality of second sheet patterns, the width of the first active pattern (CR rectangle in FIG. 2, FA section in FIG. 20) in the second direction is a width of a top surface of the first lower pattern in the second direction (first EDR section), and the width of the second active pattern (other EDR section) in the second direction is a width of a top surface of the second lower pattern in the second direction (see FIG. 20, 2). Regarding claim 11, Lee shows in FIG. 2-20, a semiconductor device, comprising: a first element separation structure (SR); a second element separation structure (second SR) spaced apart from the first element separation structure (SR) FIG. 2 shows several SR’s and FIG.20 shows SRs and separation 114) in a first direction; a first active pattern (first CR rectangle) extending in the first direction between the first element separation structure (SR) and the second element separation structure (SR); a second active pattern (other CR) extending in the first direction and separated from the first active pattern by the second element separation structure (SR); a first gate electrode (152M, GL) extending in a second direction on the first active pattern; a second gate electrode (other 152M, GL) extending in the second direction on the second active pattern (second CR); and a third gate electrode (gate 152M in CR section)(see FIG.2, and 20) extending in the second direction on the second active pattern and spaced apart from the second gate electrode in the first direction, wherein the first element separation structure (SR), the first gate electrode (152M), the second element separation structure, the second gate electrode (152M), and the third gate electrode (152M) are arranged at a first pitch [0075] along the first direction, and wherein a width of the first active pattern (first CR) in the second direction is greater than a width of the second active pattern (second CR) between the second gate electrode and the third gate electrode in the second direction (see also FIG. 20). Regarding claim 12, Lee shows in FIG. 2-20, a semiconductor device wherein the width of the first active pattern (FA in first EDR section) in the second direction is greater than or equal to a width of the second active pattern (FA section in the other EDR) between the second element separation structure (SR) and the second gate electrode in the second direction. Regarding claim 13, Lee shows in FIG. 2-20, a semiconductor device, wherein a width of the second active pattern (FA in second EDR) between the second element separation structure and the second gate electrode (152M, GL) in the second direction is greater than or equal to the width of the second active pattern between the second gate electrode and the third gate electrode (152M) in the second direction. Regarding claim 14, Lee shows in FIG. 2-20, a semiconductor device, a semiconductor device wherein: the first active pattern (first CR) (FIG. 2)includes a first sidewall and a second sidewall opposite to each other in the second direction, the second active pattern (second CR) between the second gate electrode and the third gate electrode includes a third sidewall and a fourth sidewall opposite to each other in the second direction, and the first sidewall is disposed on the same plane as the third sidewall (shown in FIG. 2). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claims 1-5,10-14, and further in view of Kang et al., (Kang) US 2020/0083219. Regarding claim 8, Lee shows in FIG. 2-20, a semiconductor device, further comprising: a first source/drain contact (184) on the first active pattern (FA). Lee differs from the claimed invention because he does not explicitly disclose a device having a second source/drain contact on the second active pattern, a length of the first source/drain contact in the second direction being equal to a length of the second source/drain contact in the second direction. Kang a device having a second source/drain contact (184) [0118] on the second active pattern, a length of the first source/drain contact (184 on other section) in the second direction being equal to a length of the second source/drain contact in the second direction. Kang is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Lee. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Kang in the device of Lee because it will facilitate electrical connections [0118]. Allowable Subject Matter Claims 6,7,9,16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 17-20 are allowed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARC - ANTHONY ARMAND Examiner Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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Prosecution Timeline

Oct 13, 2023
Application Filed
Apr 01, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
87%
With Interview (+3.9%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1054 resolved cases by this examiner. Grant probability derived from career allowance rate.

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