DETAILED ACTION
This application, 18/379841, attorney docket AM-61132, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Samsung Electronics Co., Ltd., and claims foreign priority to 10-2022-0132719, filed 10/14/2022. Claims 1-20 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 7, 10 and 11 and claim 20 are rejected under 35 U.S.C. 102A1/A2 as being anticipated by Chen et al. (U.S. 2018/0130744).
As for claim 1,
Chen teaches in figure 7F a semiconductor package comprising:
a redistribution structure (100/101/107/105) including a redistribution pattern (101) and a redistribution insulation layer (100) covering the redistribution pattern;
a semiconductor chip (103/702) disposed on the redistribution structure and having an active surface (with contacts at 130A’) and an inactive surface opposite to the active surface;
a molding layer (405) disposed on the redistribution structure and covering at least a portion of the semiconductor chip;
And a silicon heat dissipation structure (703) disposed on the semiconductor chip, wherein the silicon heat dissipation structure is bonded to the semiconductor chip through silicon (Si)-to-Si direct bonding. ([0049-0051]).
As for claim 2,
Chen teaches the semiconductor package of claim 1, and Chen teaches that the inactive surface of the semiconductor chip is hydrophilized ([0051])
As for claim 3,
Chen teaches the semiconductor package of claim 1, and teaches that a top surface of the semiconductor chip is coplanar with a top surface of the molding layer. (Examiner notes that the top surface is treated to form an oxide layer before the cooling structure is attached.)
As for claim 4,
Chen teaches the semiconductor package of claim 1, and Chen teaches a silicon oxide layer (704) between the semiconductor chip and the silicon heat dissipation structure.
As for claim 7,
Chen teaches the semiconductor package of claim 1, and teaches that the heat sink has a hydrophilized surface. [0049-0051]. The limitation, the silicon heat dissipation structure is processed from a bare silicon wafer is a product-by-process limitation which does not appear to add to the physical structure. It has been held that a product-by-process claim is directed to the product per se, regardless of how the product is actually made. In re Thorpe, 227 USPQ 964 (CAFC, 1985) and the related case law cited therein make it clear that it is the final product which must determine patentability in a product-by-process claim, and not the process by which it is made. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 162 USPQ 145 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26, USPQ 57, 61 (2d. Cir 1935) Perdue Pharma v. Epic Pharma, App. No. 2014-1294 (Fed. Cir. 2016).
As for claim 10,
Chen teaches the semiconductor package of claim 1, and teaches that the redistribution pattern comprises a redistribution line (not shown, but inherent in an RDL) and a redistribution via (103A’), and the redistribution via (103A’) has a tapered shape that a horizontal width thereof decreases in a vertical direction away from the semiconductor chip.
As for claim 11,
Chen teaches the semiconductor package of claim 1, wherein the redistribution pattern comprises a redistribution line (not shown but inherent in an RDL) and a redistribution via (101), and the redistribution via has a tapered shape that a horizontal width thereof increases in a vertical direction away from the semiconductor chip. (shown in figure 7f.
As for claim 20,
Chen teaches in figure 7H. a semiconductor package comprising:
a redistribution structure (100/103a) including a redistribution pattern (103A’,101) and a redistribution insulation layer (100) covering the redistribution pattern;
a semiconductor chip (103B/702) disposed on the redistribution structure and having an active surface (with contacts at 130A’) and an inactive surface opposite to the active surface,
wherein the inactive surface is hydrophilized ([0049-0051]);
a molding layer (405) disposed on the redistribution structure and covering at least a portion of the semiconductor chip; and
a silicon heat dissipation structure (703) disposed on the semiconductor chip,
wherein the silicon heat dissipation structure is bonded to the semiconductor chip through silicon-to-silicon direct bonding. ([0049-0051]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Brun et al. (U.S. 2023/01497664).
As for claim 5,
Chen teaches a semiconductor package with a horizontal width of the silicon heat dissipation structure 345 is identical to a horizontal width of the redistribution structure 330.
However, Brun teaches in figure 3A, a horizontal width of the silicon heat dissipation structure 345 that is identical to a horizontal width of the redistribution structure (330).
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute geometry in Brun into the device of Chen to allow a single heat sink to cover multiple chips, and still minimize the footprint of the set One skilled in the art would have combined these elements with a reasonable expectation of success.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Chee (U.S. 2024/0014099).
As for claim 6,
Chen teaches the semiconductor package of claim 1, but does not teach an air layer provided between the molding layer and the silicon heat dissipation structure.
However, Chee teaches in figure 7, an air gap (triangular portion ) between the encapsulant 106 and the heat dissipator (702)
It would have been obvious to one skilled in the art at the effective filing date of this application to include the air gap taught by Chee to the device of Chen so that the heat spreader can be can seal a device that is taller than the encapsulant 105. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen.
As for claim 8,
Chen teaches the semiconductor package of claim 1, but is silent on the thickness of the silicon heat dissipation structure is from 10 um to 755 um.
However, heat dissipator thickness is a result dependent variable that is determined by the designer who balances structural strength and thermal conduction with weight and package thickness to reach an optimum thickness. Therefore, because the general conditions are disclosed in the prior art is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). Thus, optimization of the claim would be obvious to one of ordinary skill in the art.
Claims 9, 12-15 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Koide et al. (U.S. 2011/0044015).
As for claim 9,
Chen teaches the semiconductor package of claim 1, but does not teach the redistribution structure comprises a redistribution interposer, or that the semiconductor package further comprises a package substrate under the redistribution structure.
However, Koide teaches in figure 1, a redistribution interposer (20), and a package substrate (10) under the redistribution structure.
It would have been obvious to one skilled in the art at the effective filing date of this application to add the interposer and package substrate of Koide to the device of Chen to allow multiple chips with a large number of connection points to be expanded and combined into an external set of Bumps. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 12,
Chen teaches in figure 7F, a semiconductor package comprising:
a redistribution structure (100/103) including a redistribution pattern (103/101) and a redistribution insulation layer (100) covering the redistribution pattern;
a first semiconductor chip 103/702) disposed on the redistribution structure and having a first active surface (at130a”) and a first inactive surface opposite to the first active surface;
a molding layer (405) disposed on the redistribution structure and covering at least a portion of the first semiconductor chip
and a silicon heat dissipation structure (703) disposed on the first semiconductor chip and the second semiconductor chip, wherein the silicon heat dissipation structure is bonded to the first semiconductor chip and the second semiconductor chip through silicon (Si)-to-Si direct bonding. ([0049-0051]).
Chen does not teach that the redistribution structure is disposed on the package substrate.
However, Koide teaches in figure 1, a redistribution structure (20) on a package substrate (10).
It would have been obvious to one skilled in the art at the effective filing date of this application to add the interposer and package substrate of Koide to the device of Chen to allow multiple chips with a large number of connection points to be expanded and combined into an external set of Bumps. One skilled in the art would have combined these elements with a reasonable expectation of success.
Chen does not teach a second semiconductor chip disposed on the redistribution structure and having a second active surface and a second inactive surface opposite to the second active surface;
However, Koide teaches multiple chips on the interposer.
It would have been obvious to one skilled in the art at the effective filing date of this application toad additional chips to the interposer to increase functional and capacity of the device. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 13,
Chen in view of Koide makes obvious the semiconductor package of claim 12, and in the combination, Chen teaches that the first inactive surface of the first semiconductor chip and the second inactive surface of the second semiconductor chip are hydrophilized. ([0049-0051])
As for claim 14,
Chen in view of Koide makes obvious the semiconductor package of claim 12, and in the combination, Chen teaches that a top surface of the first semiconductor chip, a top surface of the second semiconductor chip, and a top surface of the molding layer are coplanar with one another. (Examiner notes that the top surface is treated to form an oxide layer before the cooling structure is attached.)
As for claim 15,
Chen in view of Koide makes obvious the semiconductor package of claim 12, and makes obvious that any one of the first semiconductor chip and the second semiconductor chip is a logic chip, and the other one of the first semiconductor chip and the second semiconductor chip is a memory chip. (the chip type is an intended use of the circuit that would be obvious to one skilled in the art at the effective filing date of this application. t has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987). One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 18,
Chen in view of Koide makes obvious the semiconductor package of claim 12, and in the combination, Chen teaches that the redistribution pattern comprises a redistribution line (inherent in an RDL) and a redistribution via (103a’), and the redistribution via has a tapered shape that a horizontal width thereof decreases in a vertical direction away from the first and the second semiconductor chip (see figure 7H).
As for claim 19,
Chen in view of Koide makes obvious the semiconductor package of claim 12, wherein the redistribution pattern comprises a redistribution line (inherent in an RDL) and a redistribution via,(101) and the redistribution via has a tapered shape that a horizontal width thereof increases in a vertical direction away from the first and the second semiconductor chip (see figure 7H).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Koide and in further view of Brun.
As for claim 16,
Chen in view of Koide makes obvious the semiconductor package of claim 12, But the combination does not teach that a horizontal width of the silicon heat dissipation structure is identical to a horizontal width of the redistribution structure.
However, Brun teaches in figure 3A, a horizontal width of the silicon heat dissipation structure 345 that is identical to a horizontal width of the redistribution structure (330).
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute geometry in Brun into the device of Chen to allow a single heat sink to cover multiple chips, and still minimize the footprint of the set One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Koide and in further view of Chee.
As for claim 17,
Chen in view of Koide makes obvious the semiconductor package of claim 12, and in the combination, Chen teaches a silicon oxide (704) layer provided between the first semiconductor chip and the silicon heat dissipation structure and between the second semiconductor chip and the silicon heat dissipation structure; but does not teach an air layer provided between the silicon heat dissipation structure and the molding layer.
However, Chee teaches in figure 7, an air gap (triangular portion ) between the encapsulant 106 and the heat dissipator (702)
It would have been obvious to one skilled in the art at the effective filing date of this application to include the air gap taught by Chee to the device of Chen so that the heat spreader can be can seal a device that is taller than the encapsulant 105. One skilled in the art would have combined these elements with a reasonable expectation of success.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. M. M. R. Howlader, T. Suga, H. Itoh, M. J. Kim, “Sequential Plasma Activated Process for Silicon Direct Bonding,” ECS Transactions, 3 (6) 191-202 (2006). Teaches the bonding method referenced by applicant.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893