Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7, 10-12, and 14-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by S. Froehlich et al. [Towards Reversed Approximate Hardware Design”].
Taking claim 1 as exemplary of claims 1 and 11 [section VII.A.], a method for designing a circuit to perform a floating point arithmetic operation on one or more floating point operands section I. HW generation, HW design flow, a method on how to relate these to floating-point arithmetic] comprising:
identifying a plurality of parameters that characterize circuits for performing the floating point arithmetic operation [section III.A. an approximate HW design is chosen, a dedicated approximate adder or multiplier is selected] and an equation relating the plurality of parameters to a maximum relative backward error parameter, the circuits respectively corresponding to combinations of values for the parameters [section III.A. design is evaluated in terms of approximate error metrics, once the computational accuracy for the relevant operations is known its propagation to the application specific error norms can be calculated, section VII.A. we calculate the necessary computational accuracy for each matrix to get a backward error below different error bounds, Eqs. (12)-(13)];
specifying a target maximum relative backward error for the floating point arithmetic operation [section III.A. error e, application specified error bound B, section V. upper bound];
computing a maximum relative backward error for each of one or more of the combinations of values based on the equation [section III.A. design is evaluated in terms of approximate error metrics, the effect of the error induced by the approximate component on the computational accuracy of the system is evaluated, the error e is evaluated in the application specific error norm and compared to an application specified error bound B]; and
when the maximum relative backward error for a respective combination of values is less than the target maximum relative backward error [section III.A. If the result meets the bound B and is close enough to B], identifying the circuit corresponding to the maximum relative backward error as a circuit operable to perform the floating point arithmetic operation at a desirable output accuracy [section III.A. then a suitable solution based on the in the first step selected approximated components(s) has been found].
As per claims 3 and 14, wherein when the maximum relative backward error for more than one of the combinations of values is less than the target maximum relative backward error, one of the circuits corresponding to the more than one of the combinations of values is selected as a circuit to perform the floating point arithmetic operation [section III.A. If the result meets the bound B and is close enough to B, then a suitable solution based on the in the first step selected approximated components(s) has been found].
As per claims 4 and 15, wherein the selected circuit to perform the floating point arithmetic operation is the circuit having the combination of values realizing the most desirable circuit among the circuits corresponding to the more than one of the combinations of values [section III.A. If the result meets the bound B and is close enough to B, then a suitable solution based on the in the first step selected approximated components(s) has been found is interpreted as most desirable].
As per claims 5 and 16, wherein the selected circuit is selected by synthesizing the circuits for each of the more than one of the combinations of values that is less than the target maximum relative backward error to generate a plurality of synthesized circuits, and selecting the synthesized circuit that has at least one of the smallest size or the lowest power consumption per floating point operation [section I. general Synthesis and HW generation, HW design flow, section III.A. design is evaluated in terms of approximate error metrics, the effect of the error induced by the approximate component on the computational accuracy of the system is evaluated, once the computational accuracy is known is interpreted as at least one of smallest size or the lowest power consumption per floating point operation, the error e is evaluated in the application specific error norm and compared to an application specified error bound B. If the result meets the bound B and is close enough to B, then a suitable solution based on the in the first step selected approximated components(s) has been found].
As per claims 6 and 17, wherein the floating point arithmetic operation comprises an n-way addition operation to generate a floating point output, where n is an integer greater than or equal to two [section III.A. approximate adder or approximate multiplier is interpreted to provide an n-way operation].
As per claims 7 and 18, wherein the floating point arithmetic operation comprises a dot product computation [section IV. A. LU-Factorization and B. Matrix Operations].
As per claims 10 and 12, further comprising synthesizing the circuit operable to perform the floating point arithmetic operation at a desirable output accuracy [section I. general Synthesis and HW generation, HW design flow].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 8-9, 13, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over S. Froehlich et al. [Towards Reversed Approximate Hardware Design”] in view of “Floating-point arithmetic.”
As per claims 2 and 13, F. Froehlich et al. teach the features from which the claims depend. However, the reference does not teach wherein the target maximum relative backward error is less than or equal to half of a smallest representation error of the floating point operands. In Floating-point arithmetic, a range of floating-point numbers is taught, with individual arithmetic operations guaranteed accurate to within half a ULP. Thus, the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because applying a target maximum relative backward error less than or equal to half of a smallest representation error of the floating point operands results in higher accuracy.
As per claims 8 and 19, wherein the parameters comprise a precision of the floating point operands, a number of addends, a number of guard bits used for accumulation, a rounding mode, and a precision of the floating point output [Floating-point arithmetic].
As per claims 9 and 20, wherein the rounding mode is one of round to zero or round to nearest even [Floating-point arithmetic].
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see the references cited on PTO-892.
Conclusion
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/LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851
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