DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/8/2023, 1/12/2024, 3/22/2024, 9/6/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 13 is objected to because of the following informalities:
In claim 13, line 3, the limitation of “titanium allow” should be corrected into “titanium alloy”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 8-9 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mazure (US 2016/0020326) in view of Kobayashi (US 2011/0057168), and further in view of Anderson (US 2006/0267111).
Regarding claim 1, Mazure discloses, in at least figures 6A-7L and related text, a semiconductor device, comprising:
a substrate (1010, [87]);
an insulating material layer (1020, [87]), wherein a first surface (lower surface of 1020, figures) of the insulating material layer (1020, [87]) is in contact with and is disposed on a surface of the e substrate (1010, [87]);
a plurality of gate electrode layers (1401/1801, [87], [90]), wherein each gate electrode layer in the plurality of gate electrode layers (1401/1801, [87], [90]) is disposed on a second surface (upper surface of 1020, figures) of the insulating material layer (1020, [87]), and wherein the second surface (upper surface of 1020, figures) of the insulating material layer (1020, [87]) is opposite the first surface (lower surface of 1020, figures) of the insulating material layer (1020, [87]);
a plurality of channel formation region layers (1033 in 1801, [88], figures), wherein each channel formation region layer in the plurality of channel formation region layers (1033 in 1801, [88], figures) is disposed on the second surface (upper surface of 1020, figures) of the insulating material layer (1020, [87]), wherein each channel formation region layer in the plurality of channel formation region layers (1033 in 1801, [88], figures) is disposed between a unique pair of gate electrode layers of the plurality of gate electrode layers (1401/1801, [87], [90]);
a first source/drain region (1033 in region of cut-line A-A’, [88], figures), wherein the first source/drain region (1033 in region of cut-line A-A’, [88], figures) is disposed on the second surface (upper surface of 1020, figures) of the insulating material layer (1020, [87]), wherein the first source/drain region (1033 in region of cut-line A-A’, [88], figures) is in contact with a first side surface (left surface of 1033, figure 6A) of each of the channel formation region layers in the plurality of channel formation region layers (1033 in 1801, [88], figures);
a second source/drain region (1033 in region of cut-line C-C’, [88], figures), wherein the second source/drain region (1033 in region of cut-line C-C’, [88], figures) is disposed on the second surface (upper surface of 1020, figures) of the insulating material layer (1020, [87]), wherein the second source/drain region (1033 in region of cut-line C-C’, [88], figures) is in contact with a second side surface (right surface of 1033, figure 6A) of each of the channel formation region layers in the plurality of channel formation region layers (1033 in 1801, [88], figures), and wherein the first side surface (left surface of 1033, figure 6A) of the channel formation region layers (1033 in 1801, [88], figures) is opposite the second side surface (right surface of 1033, figure 6A) of the channel formation region layers (1033 in 1801, [88], figures).
Mazure does not explicitly disclose a conductive substrate; a first surface of the insulating material layer is in contact with and is disposed on a surface of the conductive substrate; a first insulating film, wherein the first insulating film is disposed on first side surfaces of each of the gate electrode layers in the plurality of gate electrode layers, and wherein the first insulating film lies between the first side surfaces of each of the gate electrode layers in the plurality of gate electrode layers and the first source/drain region; a second insulating film, wherein the second insulating film is disposed on second side surfaces of each of the gate electrode layers in the plurality of gate electrode layers, and wherein the second insulating film lies between the second side surfaces of each of the gate electrode layers in the plurality of gate electrode layers and the second source/drain region.
Kobayashi teaches, in at least figures 1A-1B and related text, the device comprising a conductive substrate (11, [61], [85]); a first surface of the insulating material layer (12, [61], [85]) is in contact with and is disposed on a surface of the conductive substrate (11, [61], [85]), for the purpose of providing electronic device having a monolithic integrated circuit in which the support body is integrated with a great number of electronic devices ([66]).
Anderson teaches, in at least figures 10A-10B and related text, the device comprising a first insulating film (1005a/620/1005b, [22], [23]), wherein the first insulating film (1005a/620/1005b, [22], [23]) is disposed on first side surfaces (upper side surfaces of 1010a/710/1010b, figure 10B) of each of the gate electrode layers in the plurality of gate electrode layers (1010a/710/1010b, [22], [24]), and wherein the first insulating film (1005a/620/1005b, [22], [23]) lies between the first side surfaces (upper side surfaces of 1010a/710/1010b, figure 10B) of each of the gate electrode layers in the plurality of gate electrode layers (1010a/710/1010b, [22], [24]) and the first source/drain region (130d, [22]); a second insulating film (1005a/620/1005b, [22], [23]), wherein the second insulating film (1005a/620/1005b, [22], [23]) is disposed on second side surfaces (lower side surfaces of 1010a/710/1010b, figure 10B) of each of the gate electrode layers in the plurality of gate electrode layers (1010a/710/1010b, [22], [24]), and wherein the second insulating film lies between the second side surfaces (lower side surfaces of 1010a/710/1010b, figure 10B) of each of the gate electrode layers in the plurality of gate electrode layers (1010a/710/1010b, [22], [24]) and the second source/drain region (130c, [22]), for the purpose of providing a device structure in which chip areas for back gates are relatively small compared to the prior art ([10]).
Mazure, Kobayashi, and Anderson are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mazure with the specified features of Kobayashi and Anderson because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Mazure to have the conductive substrate; the first surface of the insulating material layer being in contact with and being disposed on a surface of the conductive substrate, as taught by Kobayashi and the first insulating film, wherein the first insulating film is disposed on first side surfaces of each of the gate electrode layers in the plurality of gate electrode layers, and wherein the first insulating film lies between the first side surfaces of each of the gate electrode layers in the plurality of gate electrode layers and the first source/drain region; the second insulating film, wherein the second insulating film is disposed on second side surfaces of each of the gate electrode layers in the plurality of gate electrode layers, and wherein the second insulating film lies between the second side surfaces of each of the gate electrode layers in the plurality of gate electrode layers and the second source/drain region as taught by Anderson, for the purpose of providing electronic device having a monolithic integrated circuit in which the support body is integrated with a great number of electronic devices ([66], Kobayashi) and providing a device structure in which chip areas for back gates are relatively small compared to the prior art ([10], Anderson).
Regarding claim 2, Mazure in view of Kobayashi and Anderson discloses the semiconductor device of claim 1 as described above.
Mazure further discloses, in at least figures 6A-7L and related text, the plurality of gate electrode layers (left 1801/1401/right 1801, [87], [90], figure 6B) includes N gate electrode layers, wherein the plurality of channel formation region layers (left 1033/right 1033, [88], figure 6B) includes N-1 channel formation region layers, and wherein N is greater than or equal to 3.
Regarding claim 8, Mazure in view of Kobayashi and Anderson discloses the semiconductor device of claim 1 as described above.
Mazure in view of Kobayashi does not explicitly disclose a distance of a top surface of each of the gate electrode layers in the plurality of gate electrode from the second surface of the insulating material layer is greater than a distance of a top surface of each of the channel formation region layers in the plurality of channel formation region layers from the second surface of the insulating material layer.
Anderson teaches, in at least figures 10A-10B and related text, the device comprising a distance of a top surface of each of the gate electrode layers in the plurality of gate electrode (1010a/710/1010b, [22], [24]) from the second surface (upper surface of 120, figure 10A) of the insulating material layer (120, [12]) is greater than a distance of a top surface of each of the channel formation region layers in the plurality of channel formation region layers (130a/130b, [23]) from the second surface of the insulating material layer (upper surface of 120, figure 10A) of the insulating material layer (120, [12]) (figures), for the purpose of providing a device structure in which chip areas for back gates are relatively small compared to the prior art ([10]).
Mazure, Kobayashi, and Anderson are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mazure in view of Kobayashi with the specified features of Anderson because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Mazure in view of Kobayashi to have the distance of a top surface of each of the gate electrode layers in the plurality of gate electrode from the second surface of the insulating material layer being greater than a distance of a top surface of each of the channel formation region layers in the plurality of channel formation region layers from the second surface of the insulating material layer, as taught by Anderson, for the purpose of providing a device structure in which chip areas for back gates are relatively small compared to the prior art ([10], Anderson).
Regarding claim 9, Mazure in view of Kobayashi and Anderson discloses the semiconductor device of claim 1 as described above.
Mazure in view of Kobayashi does not explicitly disclose the first and second insulating films are in contact with the insulating material layer.
Anderson teaches, in at least figures 10A-10B and related text, the first (1005a/620/1005b, [22], [23]) and second (1005a/620/1005b, [22], [23]) insulating films are in contact with the insulating material layer (120, [12]), for the purpose of providing isolation for gate electrode thereby preventing leakage current.
Mazure, Kobayashi, and Anderson are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mazure in view of Kobayashi with the specified features of Anderson because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Mazure in view of Kobayashi to have the first and second insulating films being in contact with the insulating material layer, as taught by Anderson, for the purpose of providing isolation for gate electrode thereby preventing leakage current.
Regarding claim 12, Mazure in view of Kobayashi and Anderson discloses the semiconductor device of claim 1 as described above.
Mazure further discloses, in at least figures 6A-7L and related text, the source/drain regions (1033 (1030) in region of cut-line A-A’ and C-C’, [60], [88], figures) include silicon ([60]).
Claim(s) 3-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mazure (US 2016/0020326) in view of Kobayashi (US 2011/0057168), Anderson (US 2006/0267111), and further in view of Nowak (US 2006/0240610).
Regarding claim 3, Mazure in view of Kobayashi and Anderson discloses the semiconductor device of claim 2 as described above.
Mazure in view of Kobayashi and Anderson does not explicitly disclose a plurality of first contact portions, wherein each first contact portion in the plurality of first contact portions is connected to an odd-numbered layer of the gate electrode layers; one or more second contact portions, wherein each second contact portion of the one or more second contact portions is connected to an even-numbered layer of the gate electrode layers.
Nowak teaches, in at least figures 8A-8D and related text, the device comprising a plurality of first contact portions (one group of 88, [47], figure 8D), wherein each first contact portion in the plurality of first contact portions (one group of 88, [47], figure 8D) is connected to an odd-numbered layer of the gate electrode layers (30, [42], figure 8D); one or more second contact portions (another group of 88, [47], figure 8D), wherein each second contact portion of the one or more second contact portions (another group of 88, [47], figure 8D) is connected to an even-numbered layer of the gate electrode layers (30, [42], figure 8D), for the purpose of providing a dual gate fin-type field effect transistor (FinFET) structure ([10]) thereby improving controllability of carriers in channels.
Mazure, Kobayashi, Anderson, and Nowak are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mazure in view of Kobayashi and Anderson with the specified features of Nowak because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Mazure in view of Kobayashi and Anderson to have the plurality of first contact portions, wherein each first contact portion in the plurality of first contact portions is connected to an odd-numbered layer of the gate electrode layers; the one or more second contact portions, wherein each second contact portion of the one or more second contact portions is connected to an even-numbered layer of the gate electrode layers, as taught by Nowak, for the purpose of providing a dual gate fin-type field effect transistor (FinFET) structure ([10], Nowak) thereby improving controllability of carriers in channels.
Regarding claim 4, Mazure in view of Kobayashi, Anderson, and Nowak discloses the semiconductor device of claim 3 as described above.
Nowak further teaches, in at least figures 8A-8D and related text, a first wiring (84, [46]), wherein each first contact portion of the plurality of first contact portions (one group of 88, [47], figure 8D) is connected to the first wiring (84, [46]), for the purpose of providing a dual gate fin-type field effect transistor (FinFET) structure ([10]) thereby improving controllability of carriers in channels.
Regarding claim 5, Mazure in view of Kobayashi, Anderson, and Nowak discloses the semiconductor device of claim 4 as described above.
Nowak further teaches, in at least figures 8A-8D and related text, a second wiring (82, [46]), wherein each second contact portion of the one or more second contact portions (another group of 88, [47], figure 8D) is connected to the second wiring (82, [46]), for the purpose of providing a dual gate fin-type field effect transistor (FinFET) structure ([10]) thereby improving controllability of carriers in channels.
Regarding claim 6, Mazure in view of Kobayashi, Anderson, and Nowak discloses the semiconductor device of claim 3 as described above.
Nowak further teaches, in at least figures 8A-8D and related text, each of the first contact portions (one group of 88, [47], figure 8D) in connected to a top surface of each of a respective odd-numbered layer of the gate electrode layers (30, [42], figure 8D), for the purpose of providing a dual gate fin-type field effect transistor (FinFET) structure ([10]) thereby improving controllability of carriers in channels.
Regarding claim 7, Mazure in view of Kobayashi, Anderson, and Nowak discloses the semiconductor device of claim 6 as described above.
Nowak further teaches, in at least figures 8A-8D and related text, each of the second contact portions (another group of 88, [47], figure 8D) is connected to a top surface of each of a respective even-numbered layer of the gate electrode layers (30, [42], figure 8D), for the purpose of providing a dual gate fin-type field effect transistor (FinFET) structure ([10]) thereby improving controllability of carriers in channels.
Claim(s) 10-11 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mazure (US 2016/0020326) in view of Kobayashi (US 2011/0057168), Anderson (US 2006/0267111), and further in view of Kim (US 2017/0200738).
Regarding claim 10, Mazure in view of Kobayashi and Anderson discloses the semiconductor device of claim 1 as described above.
Mazure in view of Kobayashi and Anderson does not explicitly disclose the gate electrode layers include at least one of TiN, TaN, Al, TiAl, or W.
Kim teaches, in at least figures 41-42 and related text, the device comprising the gate electrode layers (120 (122/124/125), [141]-[144]) include at least one of TiN ([141]), TaN ([141]), Al ([144]), TiAl ([141]), or W ([144]), for the purpose of providing a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure ([7]).
Mazure, Kobayashi, Anderson, and Kim are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mazure in view of Kobayashi and Anderson with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Mazure in view of Kobayashi and Anderson to have the gate electrode layers including at least one of TiN, TaN, Al, TiAl, or W, as taught by Kim, for the purpose of providing a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure ([7], Kim).
Regarding claim 11, Mazure in view of Kobayashi and Anderson discloses the semiconductor device of claim 1 as described above.
Mazure in view of Kobayashi and Anderson does not explicitly disclose the gate electrode layers include TiN.
Kim teaches, in at least figures 41-42 and related text, the device comprising the gate electrode layers (120 (122/124/125), [141]-[144]) include TiN ([141]), for the purpose of providing a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure ([7]).
Mazure, Kobayashi, Anderson, and Kim are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mazure in view of Kobayashi and Anderson with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Mazure in view of Kobayashi and Anderson to have the gate electrode layers including TiN, as taught by Kim, for the purpose of providing a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure ([7], Kim).
Regarding claim 14, Mazure in view of Kobayashi and Anderson discloses the semiconductor device of claim 1 as described above.
Mazure in view of Kobayashi and Anderson does not explicitly disclose the channel formation region layers each include a channel structure portion having a nanowire structure.
Kim teaches, in at least figures 41-42 and related text, the device comprising the channel formation region layers each include a channel structure portion having a nanowire structure ([78]), for the purpose of providing a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure ([7]).
Mazure, Kobayashi, Anderson, and Kim are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mazure in view of Kobayashi and Anderson with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Mazure in view of Kobayashi and Anderson to have the channel formation region layers each including a channel structure portion having a nanowire structure, as taught by Kim, for the purpose of providing a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure ([7], Kim).
Regarding claim 15, Mazure in view of Kobayashi and Anderson discloses the semiconductor device of claim 1 as described above.
Mazure in view of Kobayashi and Anderson does not explicitly disclose the channel formation region layers each include a nanosheet structure.
Kim teaches, in at least figures 41-42 and related text, the device comprising the channel formation region layers each include a nanosheet structure ([78]), for the purpose of providing a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure ([7]).
Mazure, Kobayashi, Anderson, and Kim are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mazure in view of Kobayashi and Anderson with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Mazure in view of Kobayashi and Anderson to have the channel formation region layers each including a nanosheet structure, as taught by Kim, for the purpose of providing a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure ([7], Kim).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mazure (US 2016/0020326) in view of Kobayashi (US 2011/0057168), Anderson (US 2006/0267111), Nowak (US 2006/0240610), and further in view of Basker (US 9,881,926).
Regarding claim 13, Mazure in view of Kobayashi, Anderson, and Nowak discloses the semiconductor device of claim 3 as described above.
Mazure in view of Kobayashi, Anderson, and Nowak does not explicitly disclose the first and second contact portions include at least one of Si, an aluminum based alloy, polysilicon, copper, copper alloy, tungsten, tungsten alloy, titanium, titanium allow, WSi2, MoSi2, or TaN.
Basker teaches, in at least figure 9 and related text, the device comprising the first (left 26, col. 11/ line 36-54, figure) and second (right 26, col. 11/ line 36-54, figure) contact portions include at least one of Si, an aluminum based alloy, polysilicon, copper (col. 11/ line 36-54), copper alloy, tungsten, tungsten alloy, titanium, titanium alloy, WSi2, MoSi2, or TaN, for the purpose of providing static random access memory (SRAM) density scaling (col. 1/ line 38-47).
Mazure, Kobayashi, Anderson, Nowak, and Basker are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Mazure in view of Kobayashi, Anderson, and Nowak with the specified features of Basker because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Mazure in view of Kobayashi, Anderson, and Nowak to have the first and second contact portions including at least one of Si, an aluminum based alloy, polysilicon, copper, copper alloy, tungsten, tungsten alloy, titanium, titanium alloy, WSi2, MoSi2, or TaN, as taught by Basker, for the purpose of providing static random access memory (SRAM) density scaling (col. 1/ line 38-47, Basker).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811