DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/13/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 10, 12-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (US 2021/0358875; hereinafter Lee).
Regarding claim 1, Fig 7 of Lee discloses a semiconductor package comprising:
a first semiconductor chip (150; Fig 7; ¶ [0036]) including a first bonding layer (BO1/BO2; Fig 7; ¶ [0036]), the first bonding layer (BO1/BO2; Fig 7; ¶ [0036]) including a first chip pad (BP2; Fig 7; ¶ [0036]) and a first insulating layer (BO2/BO1; Fig 7; ¶ [0036]) covering a side surface (Fig 7) of the first chip pad;
a second semiconductor chip (140; Fig 7; ¶ [0036]) disposed below the first semiconductor chip (150; Fig 7; ¶ [0036]) and including a substrate (141; Fig 7; ¶ [0041]) having front (Top surface; Fig 7) and rear surfaces (Bottom surface; Fig 7), a second bonding layer (143A; Fig 7; ¶ [0044]) disposed on the front surface (Top surface; Fig 7) and through-electrodes (145/144B/132LC; Fig 7; ¶ [0044]) passing through the substrate (141; Fig 7; ¶ [0041]) and having protrusions (145/144B/132LC; Fig 7) protruding from the rear surface (Bottom surface; Fig 7), the second bonding layer (143A; Fig 7; ¶ [0044]) including a second chip pad (144A; Fig 7; ¶ [0095]) contacting the first chip pad (BP2; Fig 7; ¶ [0036]) and a second insulating layer (143A; Fig 7; ¶ [0095]) covering a side surface (Fig 7) of the second chip pad (144A; Fig 7; ¶ [0095]);
a redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]) disposed below the second semiconductor chip (140; Fig 7; ¶ [0036]) and electrically connected to the second semiconductor chip (140; Fig 7; ¶ [0036]);
vias (CP; Fig 7; ¶ [0048]) disposed between the redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]) and the first semiconductor chip (150; Fig 7; ¶ [0036]) and disposed around (Fig 7) the second semiconductor chip (140; Fig 7; ¶ [0036]); and
an encapsulant (MD1; Fig 7; ¶ [0036]) surrounding the second semiconductor chip (140; Fig 7; ¶ [0036]), the redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]), and the vias (CP1; Fig 7; ¶ [0048]),
wherein the encapsulant (MD1; Fig 7; ¶ [0036]) is in contact (Fig 7) with the protrusions of the through-electrodes (145/144B/132LC; Fig 7; ¶ [0044]).
Regarding claim 2, Fig 7 of Lee discloses the encapsulant (MD1; Fig 7; ¶ [0036]) fills space (Fig 7) between the protrusions (145/144B/132LC; Fig 7).
Regarding claim 3, Fig 7 of Lee discloses the encapsulant (MD1; Fig 7; ¶ [0036]) is in contact with the first bonding layer (BO1/BO2; Fig 7; ¶ [0036]) and a side surface (Fig 7) of the second semiconductor chip (140; Fig 7; ¶ [0036]).
Regarding claim 4, Fig 7 of Lee discloses the first insulating layer (BO2/BO1; Fig 7; ¶ [0036]) is in contact with the second insulating layer (143A; Fig 7; ¶ [0095]).
Regarding claim 5, Fig 7 of Lee discloses the encapsulant (MD1; Fig 7; ¶ [0036]) is in contact with the rear surface (Fig 7) of the substrate (141; Fig 7; ¶ [0041]) of the second semiconductor chip (140; Fig 7; ¶ [0036]).
Regarding claim 6, Fig 7 of Lee discloses a horizontal width (Fig 7) of the first semiconductor chip (150; Fig 7; ¶ [0036]) is greater than a horizontal width of the second semiconductor chip (140; Fig 7; ¶ [0036]).
Regarding claim 7, Fig 7 of Lee discloses a center of the second semiconductor chip (140; Fig 7; ¶ [0036]) is aligned (Fig 7) with a center of the first semiconductor chip (150; Fig 7; ¶ [0036]) and the vias (CP; Fig 7; ¶ [0048]) are arranged to surround the second semiconductor chip (140; Fig 7; ¶ [0036]).
Regarding claim 8, Fig 7 of Lee discloses the first semiconductor chip (150; Fig 7; ¶ [0036]) further includes a first circuit layer (152; Fig 7; ¶ [0041]) disposed on the first bonding layer (BO1/BO2; Fig 7; ¶ [0036]), and
the second semiconductor chip (140; Fig 7; ¶ [0036]) further includes a second circuit layer (142; Fig 7; ¶ [0041]) disposed below the second bonding layer (143A; Fig 7; ¶ [0044]) and electrically connected to the first circuit layer (152; Fig 7; ¶ [0041]).
Regarding claim 10, Fig 7 of Lee discloses a width of each of the through-electrodes (145/144B/132LC; Fig 7; ¶ [0044]) is smaller than a width of the via (CP; Fig 7; ¶ [0048]).
Regarding claim 12, Fig 7 of Lee discloses lower surfaces (Fig 7) of the through-electrodes (145/144B/132LC; Fig 7; ¶ [0044]) and lower surfaces of the vias (CP; Fig 7; ¶ [0048]) are coplanar with a lower surface of the encapsulant.
Regarding claim 13, Fig 7 of Lee discloses the redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]) includes a first wiring layer (131LC; Fig 7; ¶ [0057]), a second wiring layer (120; Fig 7; ¶ [0057]) below the first wiring layer (131LC; Fig 7; ¶ [0057]) and a via (131VC; Fig 7; ¶ [0057]) connecting the first wiring layer (131LC; Fig 7; ¶ [0057]) to the second wiring layer (120; Fig 7; ¶ [0057]).
Regarding claim 14, Fig 7 of Lee discloses the encapsulant includes at least one of a thermosetting or photocurable polymer material (¶ [0047]).
Regarding claim 15, Fig 7 of Lee discloses a semiconductor package comprising:
a first semiconductor chip (150; Fig 7; ¶ [0036]) including a first active surface (152; Fig 7; ¶ [0041]);
a second semiconductor chip (140; Fig 7; ¶ [0036]) including a second active surface (142; Fig 7; ¶ [0041]) in contact with the first active surface, the second semiconductor chip including a substrate (141; Fig 7; ¶ [0041]) having front (Top surface; Fig 7) and rear surfaces (Bottom surface; Fig 7) and a through-electrodes (145/144B/132LC; Fig 7; ¶ [0044]) passing through the substrate (141; Fig 7; ¶ [0041]) and having protrusions (145/144B/132LC; Fig 7) protruding from the rear surface (Bottom surface; Fig 7) of the substrate;
a redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]) disposed below the second semiconductor chip (140; Fig 7; ¶ [0036]) and electrically connected to the second semiconductor chip (140; Fig 7; ¶ [0036]);
vias (CP; Fig 7; ¶ [0048]) disposed between the redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]) and the first semiconductor chip (150; Fig 7; ¶ [0036]) and disposed around (Fig 7) the second semiconductor chip (140; Fig 7; ¶ [0036]); and
an encapsulant (MD1; Fig 7; ¶ [0036]) surrounding the second semiconductor chip (140; Fig 7; ¶ [0036]), the redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]), and the vias (CP1; Fig 7; ¶ [0048]),
wherein the encapsulant (MD1; Fig 7; ¶ [0036]) is in contact (Fig 7) with the protrusions of the through-electrodes (145/144B/132LC; Fig 7; ¶ [0044]).
Regarding claim 16, Fig 7 of Lee discloses an upper surface of each of the vias (CP; Fig 7; ¶ [0048]) is in contact with the first active surface (152; Fig 7; ¶ [0041]).
Regarding claim 17, Fig 7 of Lee discloses the encapsulant (MD1; Fig 7; ¶ [0036]) is in contact with the first active surface (152; Fig 7; ¶ [0041]).
First Interpretation
Regarding claim 18, Fig 7 of Lee discloses a semiconductor package comprising:
a first semiconductor chip (150; Fig 7; ¶ [0036]) including a first bonding layer (BO1; Fig 7; ¶ [0036]);
a second semiconductor chip (140; Fig 7; ¶ [0036]) disposed below the first semiconductor chip (150; Fig 7; ¶ [0036]) and including a substrate (141; Fig 7; ¶ [0041]) having front (Top surface; Fig 7) and rear surfaces (Bottom surface), a second bonding layer (143A; Fig 7; ¶ [0044]) disposed on the front surface, and through-electrodes (145/144B/132LC; Fig 7; ¶ [0044]) passing through the substrate and having protrusions protruding from the rear surface;
chip connection terminals (BP1; Fig 7; ¶ [0036]) disposed on the first semiconductor chip (150; Fig 7; ¶ [0036]) and connecting the first semiconductor chip (150; Fig 7; ¶ [0036]) to the second semiconductor chip (140; Fig 7; ¶ [0036]);
a redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]) (140; Fig 7; ¶ [0036]) and electrically connected to the second semiconductor chip (140; Fig 7; ¶ [0036]);
vias (CP; Fig 7; ¶ [0048]) disposed between the redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]) and the first semiconductor chip (150; Fig 7; ¶ [0036]) and disposed around (Fig 7) the second semiconductor chip (140; Fig 7; ¶ [0036]); and
an encapsulant (MD1/BO1; Fig 7; ¶ [0036]) surrounding the second semiconductor chip (140; Fig 7; ¶ [0036]), the redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]), and the vias (CP1; Fig 7; ¶ [0048]),
wherein the encapsulant (MD1; Fig 7; ¶ [0036]) is in contact (Fig 7) with the protrusions of the through-electrodes (145/144B/132LC; Fig 7; ¶ [0044]).
Regarding claim 19, Fig 7 of Lee discloses the encapsulant (MD1; Fig 7; ¶ [0036]) fills a space between the chip connection terminals (BP1; Fig 7; ¶ [0036]) and is in contact with the first bonding layer (BO1; Fig 7; ¶ [0036]) and the second bonding layer (143A; Fig 7; ¶ [0044]).
Second Interpretation
Regarding claim 18, Fig 7 of Lee discloses a semiconductor package comprising:
a first semiconductor chip (150; Fig 7; ¶ [0036]) including a first bonding layer (BO1; Fig 7; ¶ [0036]);
a second semiconductor chip (140; Fig 7; ¶ [0036]) disposed below the first semiconductor chip (150; Fig 7; ¶ [0036]) and including a substrate (141; Fig 7; ¶ [0041]) having front (Top surface; Fig 7) and rear surfaces (Bottom surface), a second bonding layer (143A; Fig 7; ¶ [0044]) disposed on the front surface, and through-electrodes (145/144B/132LC; Fig 7; ¶ [0044]) passing through the substrate and having protrusions protruding from the rear surface;
chip connection terminals (BP1; Fig 7; ¶ [0036]) disposed on the first semiconductor chip (150; Fig 7; ¶ [0036]) and connecting the first semiconductor chip (150; Fig 7; ¶ [0036]) to the second semiconductor chip (140; Fig 7; ¶ [0036]);
a redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]) (140; Fig 7; ¶ [0036]) and electrically connected to the second semiconductor chip (140; Fig 7; ¶ [0036]);
vias (CP; Fig 7; ¶ [0048]) disposed between the redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]) and the first semiconductor chip (150; Fig 7; ¶ [0036]) and disposed around (Fig 7) the second semiconductor chip (140; Fig 7; ¶ [0036]); and
an encapsulant (MD1; Fig 7; ¶ [0036]) surrounding the second semiconductor chip (140; Fig 7; ¶ [0036]), the redistribution layer (132VC/131LC/131VC/120; Fig 7; ¶ [0057]), and the vias (CP1; Fig 7; ¶ [0048]),
wherein the encapsulant (MD1; Fig 7; ¶ [0036]) is in contact (Fig 7) with the protrusions of the through-electrodes (145/144B/132LC; Fig 7; ¶ [0044]).
Regarding claim 20, Fig 7 of Lee discloses an adhesive layer (BO1; Fig 7; ¶ [0036]) disposed between the first bonding layer (BO1; Fig 7; ¶ [0036]) and the second bonding layer (143A; Fig 7; ¶ [0044]) and covering the chip connection terminals (BP1; Fig 7; ¶ [0036]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2021/0358875; hereinafter Lee) in view of Lin et al (US 2012/0193785; hereinafter Lin)
Regarding claim 9, Lee discloses the substrate (141; Fig 7; ¶ [0041]) comprises silicon or germanium or SiGe (¶ [0042]).
However Lee dose not expressly disclose a thickness of the substrate is about 10 µm to about 40 µm.
In the same field of endeavor, Lin discloses a thickness of the substrate comprising silicon germanium is 20 µm. (¶ [0046])
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a thickness of the substrate is within the claimed range in order to form the substrate within a suitable thickness as taught by Lin (¶ [0046]).
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2021/0358875; hereinafter Lee) in view of Shigetoshi et al (US 2024/0055326; hereinafter Shigetoshi).
Regarding claim 11, Lee does not expressly disclose a width of each of the through-electrodes is about 1 µm to about 5 µm.
In the same field of endeavor, Shigetoshi discloses a width of through-electrodes can be 3 µm (¶ [0097]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a width of through-electrodes are within the claimed range in order to form the through-electrodes of desired width so that signal transmission performance can be improved (¶ [0140]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lee et al (US 10985760; This prior art discloses package substrate and plurality of chips stacked on top of one another)
Han et al (US 2021/0013181; This prior art discloses package substrate and plurality of chips stacked on top of one another)
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817