Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gurin [US PGPUB 20160244324].
Regarding claim 11, Gurin teaches a device comprising:
a first die (110, Para 24); and
a second die (120, Para 24),
wherein the first die and the second die are stacked and form a monolithic die (Fig. 1, Para 28), wherein a first side of the first die faces a first side of the second die (Fig. 1 –i.e., at interface of first and second die),
wherein the second die comprises an electrical connection (127, Para 26) within its periphery (Fig. 1) and on a side other than the first side of the second die (Fig. 1, –i.e., side next to substrate 130), wherein the electrical connection exposes the second die to an environment outside of the die (Fig. 1, –i.e., exposure to allow for connection to substrate 130), and wherein the electrical connection is configured to facilitate electrical connection between the second die of the monolithic die and an electronic component (at least a component of substrate/PCB 130, Para 25) that is external to the die.
It is noted though that the concept monolithic die claimed and as disclosed in the specification of the application is not the traditional understanding that the first die and the second die are formed from a single wafer such as a silicon wafer. Instead, monolithic die according to the invention mean bonding a first wafer comprising plurality of first die to a second wafer comprising plurality of second die, and then singulating the stacked first and second wafer into plurality of stacked first and second die; wherein each of the plurality of stacked first and second dies is referred to as a monolithic die.
Regarding claim 16, Gurin teaches a device further comprising a substrate (130, Para 25) comprising the electronic component (wherein the substrate comprise a PCB 130, Para 25), wherein the electrical connection on the second die is a plurality of through silicon vias (TSVs) (Para 26), and wherein the electrical connection between the second die and the electrical component is formed through a solder ball (Para 26) formed between at least one TSV of the plurality of TSVs on the second die and a connection pad of the substrate (Para 26, where the CMOS die 120 may be electrically coupled to the substrate 130 via the solder and through-silicon vias (TSVs) 127 extending between the top and bottom sides of the CMOS die 120).
Claim 19 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bryzek et al. [US PGPUB 20210137497] (hereinafter Bryzek).
Regarding claim 19, Bryzek teaches a monolithic device comprising:
a micro-electro-mechanical systems (MEMS) die (902, Para 74); and
a complementary metal oxide semiconductor (CMOS) die (904, Para 70) bonded to the MEMS die forming a single integrated die (Para 16, Fig. 9),
wherein the CMOS die comprises a plurality of through silicon vias (TSVs) (leftmost and rightmost via 914, Para 70) positioned on an outer edge of the CMOS die (Fig. 9) and is exposed to an environment outside of the single integrated die (Fig. 9, –i.e., exposure to allow for connection to package 906), and
wherein the plurality of TSVs is configured to facilitate electrical connection between the CMOS die and an electronic component (906, Para 70) that is external to the single integrated die.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Gurin in view of Chou et al [US PGPUB 20170355598] (hereinafter Chou).
Regarding claim 12, Gurin teaches a device wherein the first die is a micro-electro-mechanical systems (MEMS) die (Para 24) and wherein the second die is a complementary metal oxide semiconductor (CMOS) die (Para 24).
Gurin does not specifically disclose wherein the MEMS die comprises a MEMS cap layer that is coupled to a MEMS device layer.
Referring to the invention of Chou, Chou discloses an exemplary structure of a MEMS and CMOS die stack (Fig. 9), and wherein the MEMS die (116/130, Para 22) comprises a MEMS cap layer (Para 22) that is coupled to a MEMS device layer (116, Para 22, Fig. 9).
In view of such teaching by Chou, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Gurin comprise the teaching of Chou at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results or improve similar device in the same way (MPEP 2143.I.B).
Regarding claim 13, the modified invention of Gurin specifically in view of Chou teaches a device wherein the MEMS device layer comprises movable structures including a proof mass (122a, Para 18).
Regarding claim 14, the modified invention of Gurin specifically in view of Chou teaches a device wherein the MEMS cap layer forms at least a cavity (902, Para 52) when coupled to the MEMS device layer (Fig. 9).
Regarding claim 15, the modified invention of Gurin specifically in view of Chou teaches a device wherein the MEMS die is a sensor for measuring gyro or acceleration (claim 9).
Claims 18 are rejected under 35 U.S.C. 103 as being unpatentable over Gurin in view of Smeys et al. [US PGPUB 20180009654] (hereinafter Smeys).
Regarding claim 18, Gurin teaches the limitation of claim 18 upon which it depends.
Gurin does not specifically disclose a device wherein the monolithic die is formed by eutectic bonding the first die to the second die.
Referring to the invention of Smeys, Smeys discloses the bonding of MEMS device. CMOS devices, and a substrate (Fig. 1), wherein the devices are connected electrically and mechanically by using one of or in combination of various bonding processes to included eutectic bonding (Para 31).
In view of such teaching by Smeys, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Gurin comprise the teaching of Smeys at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gurin in view of Zundel et al. [US PGPUB 20170076961] (hereinafter Zundel).
Regarding claim 17, Gurin teaches the limitation of claim 16 upon which it depends.
Gurin does not specifically disclose a device wherein at least one TSV of the plurality of TSVs is cube shaped.
Referring to the invention of Zundel, Zundel discloses TSV 116 (Para 63) passing through die 102, and wherein the TSV could any of various shapes to include a cube shape.
In view of such teaching by Zundel, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention Gurin comprise the teaching of Zundel at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bryzek in view Zundel.
Regarding claim 20, Bryzek teaches the limitation of claim 19 upon which it depends.
Bryzek does not specifically disclose a monolithic device wherein the plurality of TSVs is cube shaped.
Referring to the invention of Zundel, Zundel discloses TSV 116 (Para 63) passing through die 102, and wherein the TSV could any of various shapes to include a cube shape.
In view of such teaching by Zundel, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention Bryzek comprise the teaching of Zundel at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Allowable Subject Matter
Claims 1-10 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1-10 are allowed because all prior arts of record and related prior arts not of record either singularly or in combination fail to anticipate or render obvious a method comprising:
wherein the separating exposes at least one or more TSVs of the plurality of TSVs of the first CMOS die to an environment outside of the first monolithic die,
wherein the separating exposes at least one or more TSVs of the plurality of TSVs of the second CMOS die to the environment outside of the second monolithic die (as claimed in claim 1), in combination with the rest of claim limitations as claimed and defined by the Applicant.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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