Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 13 recites the limitation "the dielectric layer" in line 1. There is insufficient antecedent basis for this limitation in the claim. For examination purpose, claim 13 would be understood to depend on claim 9.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-15, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. [US PGPUB 20190237623] in view of Choi et al. [US PGPUB 20120018764] and in view of Cho et al. [US PGPUB 20140209956] (hereinafter Sung, Choi, and Cho).
Regarding claim 1, Sung teaches a light-emitting structure, comprising:
a substrate (170, Fig. 1 according to the modified structure indicated in Fig. 9, Para 109), and
a first metal layer (165/162-1, Fig. 1/9, Para 175), an insulating layer (131, Para 145), an integrated metal layer (150, Para 105; wherein the layer is structurally capable of being referred to as an integrated metal layer), and a semiconductor stack (120, Para 84), disposed above the substrate (Fig. 1);
wherein the semiconductor stack comprises a first-type semiconductor layer (124, Para 87), an active region (126, Para 84), and a second-type semiconductor layer (127, Para 90), stacked in sequence along a direction (Fig. 1. vertical direction), the direction being perpendicular to the substrate and being directed from the semiconductor stack to the substrate (Fig. 1),
wherein the semiconductor stack has a through hole (128, Para 91) exposing a part of a surface of the first- type semiconductor layer (Fig. 1),
wherein the integrated metal layer is disposed on a surface of the second-type semiconductor layer facing away from the active region (Fig. 1), and the integrated metal layer comprises an exposed surface on a side of the integrated metal layer facing the second-type semiconductor layer (Fig. 1);
wherein the insulating layer is disposed on a side of the semiconductor stack facing the substrate (Fig. 1), covers the integrated metal layer and an exposed surface of the semiconductor stack (Fig. 1);
wherein the first metal layer is stacked on a surface of the insulation layer facing away from the integrated metal layer (Fig. 1), embedded in the through hole to form contact with the first-type semiconductor layer (Fig. 1), and insulated from a sidewall of the through hole (Fig. 1); and
wherein the substrate is stacked on a surface of the first metal layer facing away from the stack.
Sung does not specifically disclose that the semiconductor stack is an epitaxial stack, and that the exposed surface of the integrated metal layer being configured to electrically connect with an external driving device.
However, a person having ordinary skills in the art will find it at least obvious that since exposed surface of the integrated metal layer 150 is connected to pad 166, and that the second electrode pad 166, the second conductive layer 150, and the second electrode 246 may form one electrical channel (Para 104), the exposed surface of the integrated metal layer will be configured to electrically connect with an external driving device.
Referring to the invention of Choi, Choi teaches an electrode pad portion 147 may be provided in the exposed region 145 in order to connect an external power supply to the second electrode layer 140 (Para 80).
In view of such teaching by Choi, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Sung comprise the teaching of Choi at least based on the rationale of applying a known technique to a known device (method, or product) to yield predictable results (MPEP 2143.I.D).
Referring to the invention of Cho, Cho teaches a semiconductor stack 20 (light emitting structure, Para 56), and wherein the stack can be formed by various methods to include epitaxial process (Para 58).
In view of such teaching by Cho, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Sung comprise the teaching of Cho at least based on the rationale of applying a known technique to a known device (method, or product) to yield predictable results (MPEP 2143.I.D).
Regarding claim 2, Sung teaches a light-emitting structure wherein the integrated metal layer is made of any one or any combination of Au, copper, palladium, or aluminum (Para 106).
Regarding claim 3, Sung teaches a light-emitting structure wherein a sidewall of the integrated metal layer is covered by the insulating layer (Fig. 1).
Regarding claim 4, Sung teaches a light-emitting structure further comprising:
an ohmic reflective layer (246, Para 94; ohmic at least in view of materials disclosed or at least in view of the fact that all the materials disclosed have reflectivity to a certain degree), disposed on a surface of the integrated metal layer facing the second-type semiconductor layer (Fig. 1), the ohmic reflective layer is configured to perform ohmic contact and realize light reflection (Para 94).
Regarding claim 5, Sung teaches a light-emitting structure wherein the ohmic reflective layer is made of any one or any combination of indium tin oxide, zinc tin oxide, indium zinc tin oxide, indium aluminum tin oxide, indium gallium tin oxide, aluminum zinc oxide, antimony tin oxide, gallium zinc oxide, IrOx, RuOx, indium, tin, aluminum, Au, platinum, zinc, silver, titanium, lead, nickel, rhodium, or molybdenum (Para 94).
Regarding claim 6, Sung teaches a light-emitting structure wherein the substrate comprises a conductive substrate (Para 109).
Regarding claim 7, Sung teaches a light-emitting structure further comprising: a passivation layer (180, Para 98), disposed on a sidewall of the epitaxial stack (Fig. 1).
Regarding claim 8, Sung teaches a light-emitting structure wherein the insulating layer extends to the sidewall of the through hole, so that the first metal layer is insulated from the sidewall of the through hole (Fig. 1).
Regarding claim 9, Sung teaches a light-emitting structure further comprising:
a dielectric layer (131, Para 145), stacked on a surface of the second-type semiconductor layer facing away from the active region (Fig. 1), and
a metal reflective layer (246, Para 94), in contact with the second-type semiconductor layer through an opening embedded in the dielectric layer (Fig. 1);
wherein the integrated metal layer is stacked on a surface of the metal reflective layer facing away from the epitaxial stack (Fig. 1).
Regarding claim 10, Sung teaches a light-emitting structure wherein the dielectric layer has m openings, wherein m is a positive integer not less than 2 (Fig. 3).
Regarding claim 11, Sung teaches a light-emitting structure comprising n through holes, wherein n is a positive integer not less than 2 (Fig. 1).
Regarding claim 12, Sung teaches a light-emitting structure further comprising:
a filling structure (160, Fig. 1/9, Para 108), disposed in the through hole, wherein the filling structure comprises independent epitaxial pillars formed by etching in the epitaxial stack, or the filling structure comprises any one or any combination of insulating materials and metals (Para 108).
Regarding claim 13, Sung teaches a light-emitting structure wherein the dielectric layer comprises any one or any combination of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, an aluminum oxide layer, a magnesium fluoride layer, or a hafnium oxide layer (Para 102).
Regarding claim 14, Sung teaches a light-emitting structure wherein the metal reflective layer comprises any one or any combination of an aluminum metal layer, a silver metal layer, an Au metal layer, a platinum metal layer, a lead metal layer, a nickel metal layer, an indium metal layer, a zinc metal layer, a chromium metal layer, a niobium metal layer, a titanium metal layer, a tin metal layer, or a rhodium metal layer (Para 94).
Regarding claim 15, Sung teaches a light-emitting structure wherein the first-type semiconductor layer has a roughened surface on a side facing away from the active region (Fig. 1).
Regarding claim 17, Sung teaches a light-emitting structure further comprising: a passivation layer (180, Para 98), disposed on a sidewall of the epitaxial stack (Fig. 1).
Regarding claim 20, Sung teaches a light-emitting device, comprising:
a driving signal to a light-emitting structure (inherent to power the light-emitting structure, Para 141); and
the light-emitting structure, comprising:
a substrate (170, Fig. 1 according to the modified structure indicated in Fig. 9, Para 109), and
a first metal layer (165/162-1, Fig. 1/9, Para 175), an insulating layer (131, Para 145), an integrated metal layer (150, Para 105, wherein the layer is structurally capable of being referred to as an integrated metal layer), and a semiconductor stack (120, Para 84), disposed above the substrate (Fig. 1);
wherein the semiconductor stack comprises a first-type semiconductor layer (124, Para 87), an active region (126, Para 84), and a second-type semiconductor layer (127, Para 90), stacked in sequence along a direction (Fig. 1. vertical direction), the direction being perpendicular to the substrate and being directed from the semiconductor stack to the substrate (Fig. 1),
wherein the semiconductor stack has a through hole (128, Para 91) exposing a part of a surface of the first- type semiconductor layer (Fig. 1),
wherein the integrated metal layer is disposed on a surface of the second-type semiconductor layer facing away from the active region (Fig. 1), and the integrated metal layer comprises an exposed surface on a side of the integrated metal layer facing the second-type semiconductor layer (Fig. 1);
wherein the insulating layer is disposed on a side of the semiconductor stack facing the substrate (Fig. 1), covers the integrated metal layer and an exposed surface of the semiconductor stack (Fig. 1);
wherein the first metal layer is stacked on a surface of the insulation layer facing away from the integrated metal layer (Fig. 1), embedded in the through hole to form contact with the first-type semiconductor layer (Fig. 1), and insulated from a sidewall of the through hole (Fig. 1); and
wherein the substrate is stacked on a surface of the first metal layer facing away from the stack.
Sung does not specifically disclose that a driving device, configured to transmit a driving signal to a light-emitting structure;
the semiconductor stack is an epitaxial stack, and
that the exposed surface being configured to electrically connect with an external driving device.
However, a person having ordinary skills in the art will find it at least obvious that since exposed surface of the integrated metal layer 150 is connected to pad 166, and that the second electrode pad 166, the second conductive layer 150, and the second electrode 246 may form one electrical channel (Para 104), the exposed surface of the integrated metal layer will be configured to electrically connect with an external driving device.
Referring to the invention of Choi, Choi teaches an electrode pad portion 147 may be provided in the exposed region 145 in order to connect an external power supply to the second electrode layer 140 (Para 80).
In view of such teaching by Choi, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Sung comprise the teaching of Choi at least based on the rationale of applying a known technique to a known device (method, or product) to yield predictable results (MPEP 2143.I.D).
Referring to the invention of Cho, Cho teaches a semiconductor stack 20 (light emitting structure, Para 56), and wherein the stack can be formed by various methods to include epitaxial process (Para 58).
In view of such teaching by Cho, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Sung comprise the teaching of Cho at least based on the rationale of applying a known technique to a known device (method, or product) to yield predictable results (MPEP 2143.I.D).
Claim 1-3, 6-9, 13-15, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hoppel [US PGPUB 20130228798] in view of Choi.
Regarding claim 1, Hoppel teaches a light-emitting structure, comprising:
a substrate (9, Fig. 1Q, Para 44), and
a first metal layer (6, Para 60), an insulating layer (12 or 5/12, Para 39/43), an integrated metal layer (7, Para 42), and an epitaxial stack (1-3, Para 51), disposed above the substrate (1Q);
wherein the epitaxial stack comprises a first-type semiconductor layer (1, Para 39), an active region (3, Para 39), and a second-type semiconductor layer (2, Para 39), stacked in sequence along a direction (vertical direction, Fig. 1Q), the direction being perpendicular to the substrate and being directed from the epitaxial stack to the substrate (Fig. 1Q),
wherein the epitaxial stack has a through hole (8, Para 59) exposing a part of a surface of the first-type semiconductor layer (Fig. 1Q),
wherein the integrated metal layer is disposed on a surface of the second-type semiconductor layer facing away from the active region (Fig. 1Q), and the integrated metal layer comprises an exposed surface on a side of the integrated metal layer facing the second-type semiconductor layer (Fig. 1Q), the exposed surface being configured to contact a contact wire (Para 42);
wherein the insulating layer is disposed on a side of the epitaxial stack facing the substrate (Fig. 1Q), covers the integrated metal layer and an exposed surface of the epitaxial stack (Fig. 1Q; meaning that it doesn’t completely encapsulates the integrated metal layer or encapsulates the epitaxial stack);
wherein the first metal layer is stacked on a surface of the insulation layer facing away from the integrated metal layer (Fig. 1Q), embedded in the through hole to form contact with the first-type semiconductor layer (Fig. 1Q), and insulated from a sidewall of the through hole (Fig. 1Q; insulated by material 2’’ and 5, Para 39/40); and
wherein the substrate is stacked on a surface of the first metal layer facing away from the epitaxial stack (Fig. 1Q).
Hoppel does not specifically disclose that the exposed surface integrated metal layer being configured to electrically connect with an external driving device.
However, a person having ordinary skills in the art will find it at least obvious that since exposed surface of the integrated metal layer 150 is connected to pad 166, and that the second electrode pad 166, the second conductive layer 150, and the second electrode 246 may form one electrical channel (Para 104), the exposed surface of the integrated metal layer will be configured to electrically connect with an external driving device.
Referring to the invention of Choi, Choi teaches an electrode pad portion 147 may be provided in the exposed region 145 in order to connect an external power supply to the second electrode layer 140 (Para 80).
In view of such teaching by Choi, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Sung comprise the teaching of Choi at least based on the rationale of applying a known technique to a known device (method, or product) to yield predictable results (MPEP 2143.I.D).
Regarding claim 2, Hoppel teaches a light-emitting structure wherein the integrated metal layer is made of any one or any combination of Au, copper, palladium, or aluminum (Para 42).
Regarding claim 3, Hoppel teaches a light-emitting structure wherein a sidewall of the integrated metal layer is covered by the insulating layer (Fig. 1Q).
Regarding claim 6, Hoppel teaches a light-emitting structure wherein the substrate comprises a conductive substrate (Para 44).
Regarding claim 7, Hoppel teaches a light-emitting structure further comprising: a passivation layer (15, Para 46), disposed on a sidewall of the epitaxial stack (Fig. 1Q).
Regarding claim 8, Hoppel teaches a light-emitting structure wherein the insulating layer extends to the sidewall of the through hole, so that the first metal layer is insulated from the sidewall of the through hole (Fig. 1Q –wherein the insulating layer is layer 5/12).
Regarding claim 9, Hoppel teaches a light-emitting structure further comprising:
a dielectric layer (5/15, Para 46/55, Fig. 1Q), stacked on a surface of the second-type semiconductor layer facing away from the active region (Fig. 1O/Q), and
a metal reflective layer (4, Abstract), in contact with the second-type semiconductor layer through an opening embedded in the dielectric layer (Fig. 1Q);
wherein the integrated metal layer is stacked on a surface of the metal reflective layer facing away from the epitaxial stack (Fig. 1Q).
Regarding claim 13, Hoppel teaches a light-emitting structure wherein the dielectric layer comprises any one or any combination of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a titanium oxide layer, an aluminum oxide layer, a magnesium fluoride layer, or a hafnium oxide layer (Para 46).
Regarding claim 14, Hoppel teaches a light-emitting structure wherein the metal reflective layer comprises any one or any combination of an aluminum metal layer, a silver metal layer, an Au metal layer, a platinum metal layer, a lead metal layer, a nickel metal layer, an indium metal layer, a zinc metal layer, a chromium metal layer, a niobium metal layer, a titanium metal layer, a tin metal layer, or a rhodium metal layer (Para 39).
Regarding claim 15, Hoppel teaches a light-emitting structure wherein the first-type semiconductor layer has a roughened surface on a side facing away from the active region (Fig. 1Q).
Regarding claim 17, Hoppel teaches a light-emitting structure further comprising: a passivation layer (material 2’’, Para 40, Fig. 1Q), disposed on a sidewall of the epitaxial stack (Fig. 1Q).
Regarding claim 18, Hoppel teaches a light-emitting structure wherein the metal reflective layer extends to the sidewall of the through hole by being attached to the dielectric layer, and the insulating layer covers a surface of the metal reflective layer (Fig. 1Q).
Regarding claim 20, Hoppel teaches a light-emitting device,
a driving signal to a light-emitting structure (inherent to power the light-emitting structure, Fig. 1Q,); and
the light-emitting structure, comprising:
a substrate (9, Fig. 1Q, Para 44), and
a first metal layer (6, Para 60), an insulating layer (12 or 5/12, Para 39/43), an integrated metal layer (7, Para 42), and an epitaxial stack (1-3, Para 39), disposed above the substrate (1Q);
wherein the epitaxial stack comprises a first-type semiconductor layer (1, Para 39), an active region (3, Para 39), and a second-type semiconductor layer (2, Para 39), stacked in sequence along a direction (vertical direction, Fig. 1Q), the direction being perpendicular to the substrate and being directed from the epitaxial stack to the substrate (Fig. 1Q),
wherein the epitaxial stack has a through hole (8, Para 59) exposing a part of a surface of the first- type semiconductor layer (Fig. 1Q),
wherein the integrated metal layer is disposed on a surface of the second-type semiconductor layer facing away from the active region (Fig. 1Q), and the integrated metal layer comprises an exposed surface on a side of the integrated metal layer facing the second-type semiconductor layer (Fig. 1Q), the exposed surface being configured to contact a contact wire (Para 42);
wherein the insulating layer is disposed on a side of the epitaxial stack facing the substrate (Fig. 1Q), covers the integrated metal layer and an exposed surface of the epitaxial stack (Fig. 1Q; meaning that it doesn’t completely encapsulates the integrated metal layer or encapsulates the epitaxial stack);
wherein the first metal layer is stacked on a surface of the insulation layer facing away from the integrated metal layer (Fig. 1Q), embedded in the through hole to form contact with the first-type semiconductor layer (Fig. 1Q), and insulated from a sidewall of the through hole (Fig. 1Q; insulated by material 2’’ and 5, Para 39/40); and
wherein the substrate is stacked on a surface of the first metal layer facing away from the epitaxial stack (Fig. 1Q).
Hoppel does not specifically disclose a driving device, configured to transmit a driving signal to a light-emitting structure, and that
the exposed surface integrated metal layer being configured to electrically connect with an external driving device.
However, a person having ordinary skills in the art will find it at least obvious that since exposed surface of the integrated metal layer 150 is connected to pad 166, and that the second electrode pad 166, the second conductive layer 150, and the second electrode 246 may form one electrical channel (Para 104), the exposed surface of the integrated metal layer will be configured to electrically connect with an external driving device.
Referring to the invention of Choi, Choi teaches an electrode pad portion 147 may be provided in the exposed region 145 in order to connect an external power supply to the second electrode layer 140 (Para 80).
In view of such teaching by Choi, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Sung comprise the teaching of Choi at least based on the rationale of applying a known technique to a known device (method, or product) to yield predictable results (MPEP 2143.I.D).
Allowable Subject Matter
Claim16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812