2023DETAILED ACTION
The present application, filed on 10/13/2023, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are being examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites
“wherein the DC bias varies at intervals of a third cycle between a first DC voltage and a second DC voltage, wherein each of the first DC voltage and the second DC voltage are lower than the reference voltage, and wherein the third cycle is longer than the second cycle”.
It is noted however that according to the abstract, first cycle relates to pulse power 560 and second cycle relates to RF power 550. Abstract mentions third cycle but it does not appear to relate to DC bias voltage applied to upper electrode.
DC bias is disclosed in Fig 12. However, third cycle is not displayed in this drawing. In fact, first, second and third cycles are not displayed in any drawing.
It is requested that these cycle markers are displayed on all the drawings and explained in the specification to clarify the relationship of durations and cycle in each instance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8, 11-12 and 14-15 are rejected under 35 U.S.C. 103 as beast understood, being unpatentable over Tokashiki et al (US 2016/0064194) in view of Nagami et al (US 20190333741)
Tokashiki teach a semiconductor processing apparatus comprising:
a process chamber (Fig. 1, 510) in which a semiconductor process is performed;
a lower electrode (520) disposed inside the process chamber, the lower electrode 520 having a top surface on which a substrate 100 is loaded;
an upper electrode (530);
a first power generator (RF power generator – Fig. 1, 550) configured to provide a RF signal to the lower electrode. It is noted that RF power waveform oscillates between a higher and a lower voltage than zero voltage which is the reference voltage (Fig 6 and 10).
a second power generator (560) configured to provide a square wave signal to the lower electrode.
a direct-current (DC) power generator (570) configured to provide a DC bias to the upper electrode 530. The DC voltage could be lower than the Vref (Fig 6 and 8).
Low frequency and high frequency signals have alternative turn-ON and turn-OFF state.
Tokashiki et al do not disclose that the square wave signal oscillates between Reference voltage (zero V) and a third voltage lower than zero, meaning negative and that low frequency square wave and high frequency signals are so synchronized that turn-ON signal of high frequency and turn OFF signal of low frequency are in the same duration and turn-OFF signal of high frequency and turn-ON signal of low frequency are also in the same time duration.
It is noted from the specification and drawings that Vref is Voltage 0 which would be the case when RF power supply is turned OFF.
Nagami et al disclose a pulsed DC (Fig 1, 70) and two high frequencies connected to the lower electrode (61 and 62). The duty cycle of the pulse DC is regulated (Para [0006]).
As shown in Fig 8B first high frequency is turned on for the duration (S1 corresponds to D2) when the Pulse DC is at 0 volts (T2 corresponds to D4) which is same as the Vref in the application. The high frequency is turned OFF (S2 corresponds to D1) when DC volts is negative (or lower than the reference voltage and corresponds to D3).
It would be obvious to synchronize RF power and DC bias to lower electrode as taught by Nagami et al for optimization of ion energy for process in Tokashiki et al.
Regarding claim 2-3 the description using Fig 8B discloses this.
Regarding claim 4 first cycle refers to high frequency and the time for one wave is clearly much shorter than the cycle of the square wave (See Tokashiki Fig 6).
Regarding claims 5, 6, 14 and 15 first and second durations are controlled according to duty ratio which could be from less than 50% to more than 50% as in Fig 8A and 8B or from 25% to 75% as in Fig 16A-20E.
Regarding claim 7 DC bias assumes values VD1 and VD2 both below reference voltage 0 (Tokashiki at Fig 8). The cycle time is disclosed in Fig 10 and 11.
Claim 8 is rejected with claim 1.
Regarding claims 11-12 durations of RF and DC are synchronized as in Fig 8B.
Claims 9-10, 13 and 16-20 are rejected under 35 U.S.C. 103 as beast understood, being unpatentable over Tokashiki et al (US 2016/0064194) in view of Nagami et al (US 20190333741) and LIAO et al (US 20110031216).
Claim 9 appears to pertain to Fig 4 which is similar to the embodiment of Fig 3 as discussed above, except the square wave phase is sifted by 90o. As noted in Tokashiki combination of different power supplies allows generation of particular bias wave forms (Fig 3-5) which provide improvement of semiconductor fabrication process (Abstract) by controlling ion energy (Para 69, 84, 96 and 102). This points to different configurations of waveforms for different process requirements. Claim 9 recites power supplies in a different configuration capable of being executed in the cited prior art as above, but not disclosed explicitly.
LIAO et al disclose a semiconductor processing apparatus comprising:
a process chamber (Fig. 1, 110) in which a semiconductor process is performed;
a lower electrode (136) disposed inside the process chamber, the lower electrode having a top surface on which a substrate 137 is loaded;
an upper electrode (108);
a first power generator (RF power generator – Fig. 1, 146 or 149) configured to provide a RF signal to the lower electrode and a second power generator (162) configured to provide a DC pulse signal to the lower electrode.
LIAO et al disclose different waveforms in Fig 2A-2C and teach that there could be phase variance (Abstract) and duty cycle between different power supply signals. (Fig 3A-3D and 4A-4B). LIAO et al teach that this capability allows ion energy to be controlled (Para 37)
Therefore, having a configuration as claimed would have been obvious for one of ordinary skill in the art before the effective filing date of this invention in order to control semiconductor fabrication process.
Claim 10 as claim 9 refers to Fig 4 and is rejected for the same reason.
Claim 13 and 18 appear to refer to Fig 7 which implies duty ratio being different from 50%. As discussed above, duty ratio control is disclosed by LIAO (Abstract and at least para 37) in order to control ion energy.
Claim 16 includes all the limitations of claim 1 and claim 13 as pointing to duty ration being different from 50% and is being rejected as above.
Claim 17 appears to refer to Fig 3 and is therefore rejected with claim 1.
Regarding claim 19 reference voltage is zero in Tokashiki and Nagami and is same.
Claim 20 is directed to a functional limitation, however high frequency signal helps generate plasma and low frequency signal generates bias to develop ion energy as disclosed (Liao Para 37).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hirano (US 2016/0079037) teach a plasma apparatus comprising upper and lower electrodes, low and high frequency power supplies connected to lower electrode and a DC power supply connected to upper electrode (Fig. 1). Hirano also teach pulsing of low and high frequency powers (e.g. Fig. 2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAM N KACKAR whose telephone number is (571)272-1436. The examiner can normally be reached 09:00 AM-05:00 PM.
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RAM N. KACKAR
Primary Examiner
Art Unit 1716
/RAM N KACKAR/Primary Examiner, Art Unit 1716
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