DETAILED ACTION
This action is responsive to the application No. 18/380,303 filed on October 16, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The application filed on 10/16/2023 has been entered. Accordingly, pending in this Office action are claims 1-11.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi (US 2023/0237937).
Regarding Claim 1, Choi (see, e.g., Figs. 5, 8, 10, 12, 15, and Annotated Fig. 8), teaches a display device, comprising:
a first substrate SUB including an active area DA and a non-active area NDA, the non-active area NDA including a plurality of first areas A1 spaced apart from each other and a plurality of second areas A2 disposed between the plurality of first areas A1 (see, e.g., pars. 0084, 0097, 0156);
a plurality of first pad electrodes PAD disposed on the plurality of first areas A1 (see, e.g., par. 0097);
a plurality of side lines SCL disposed on the plurality of first pad electrodes PAD (see, e.g., par. 0156); and
a plurality of step compensation layers PAS1/OC disposed in the plurality of second areas A2 (see, e.g., pars. 0171, 0237).
Regarding Claim 2, Choi teaches all aspects of claim 1. Choi (see, e.g., Figs. 5, 8, 10, 12, 15, and Annotated Fig. 8), teaches a first planarization layer ILD disposed between the first substrate SUB and the plurality of step compensation layers PAS1/OC in the plurality of second areas A2 (see, e.g., pars. 0170).
Regarding Claim 3, Choi teaches all aspects of claim 2. Choi (see, e.g., Figs. 5, 8, 10, 12, 15, and Annotated Fig. 8), teaches that each of the plurality of first pad electrodes PAD includes:
a first conductive layer PAD1 disposed on the first substrate SUB (see, e.g., par. 0188);
a second conductive layer PAD2 disposed on the first conductive layer PAD1 (see, e.g., par. 0195); and
a third conductive layer PAD3 disposed on the second conductive layer PAD2 and the first planarization layer ILD (see, e.g., par. 0200).
Regarding Claim 4, Choi teaches all aspects of claim 3. Choi (see, e.g., Figs. 5, 8, 10, 12, 15, and Annotated Fig. 8), teaches:
a second planarization layer VIA1 disposed on the first planarization layer ILD, wherein the first planarization layer ILD is disposed in the active area DA and the plurality of second areas A2 (see, e.g., par. 0170), and
the second planarization layer VIA1 is disposed in the active area DA and spaced apart from the third conductive layer PAD3.
Regarding Claim 5, Choi teaches all aspects of claim 4. Choi (see, e.g., Figs. 5, 8, 10, 12, 15, and Annotated Fig. 8), teaches that a planar shape of an edge of the first planarization layer ILD has an uneven structure (i.e., portion where via connecting first conductive pad layer PAD1 and fan-out line FOL penetrates ILD layer in NDA).
Regarding Claim 6, Choi teaches all aspects of claim 1. Choi (see, e.g., Figs. 5, 8, 10, 12, 15, and Annotated Fig. 8), teaches:
a side insulating layer CTL covering the plurality of side lines SCL and the plurality of step compensation layers PAS1/OC (see, e.g., par. 0276); and
an optical film FL disposed on the side insulating layer CTL (see, e.g., par. 0276, 0278).
Regarding Claim 7, Choi teaches all aspects of claim 6. Choi (see, e.g., Figs. 5, 8, 10, 12, 15, and Annotated Fig. 8), teaches that one surface of the optical film FL overlapping the plurality of second areas A2 is all in contact with the side insulating layer CTL.
Allowable Subject Matter
Claims 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/Primary Examiner, Art Unit 2814