Prosecution Insights
Last updated: July 17, 2026
Application No. 18/380,305

ARRAY SUBSTRATE, PREPARATION METHOD THEREOF, DISPLAY PANEL, AND DISPLAY DEVICE

Non-Final OA §103
Filed
Oct 16, 2023
Priority
Jun 30, 2023 — CN 202310798779.5
Examiner
PATEL, REEMA
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tianma Advanced Display Technology Institute (Xiamen) Co., Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
996 granted / 1122 resolved
+20.8% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
34 currently pending
Career history
1156
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
61.4%
+21.4% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
11.8%
-28.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1122 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I (encompassing claims 1-17) in the reply filed on 2/4/26 is acknowledged. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) was submitted on 10/16/23. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 5, 7-12, 15, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (U.S. 2021/0202668 A1; “Kwon”) in view of Chen et al. (U.S. 2021/0367119 A1; “Chen”) as evidenced by teaching reference Mat (“Copper Mineral Properties, Uses and Occurrences”, GeologyScience.com, 3/14/2023). Regarding claim 1, Kwon discloses an array substrate, comprising: A substrate (400, Fig. 6) ([0173]); An alignment mark (350, Fig. 6) disposed on a side of the substrate ([0175]); A mark covering layer (403, Fig. 6) disposed on a side of the alignment mark facing away from the substrate, wherein the mark covering layer (403, Fig. 6) at least partially overlaps the alignment mark (350, Fig. 6) ([0177]); and A signal line layer (630, Fig. 6), and the signal line layer (630, Fig. 6) is in contact with the mark covering layer (403, Fig. 6) and exposes at least a portion of the mark covering layer (403, Fig. 6) ([0179]). Yet, Kwon does not disclose the signal line layer is a light-shielding layer, wherein a transmittance of the light-shielding layer is less than a transmittance of the mark covering layer. However, Chen discloses a signal line layer may comprise copper ([0050]). Copper has the advantage of good electrical conductivity which would advantageously improve device performance. Teaching reference Mat discloses that copper is opaque (“Optical Properties”, pp 5) so the signal line layer of Kwon in view of Chen can be considered a “light-shielding layer” and the transmittance of the signal line layer or light-shielding layer can be considered to be less than a transmittance of the mark covering layer since the signal line layer or light-shielding layer is opaque, whereas the mark covering layer (Kwon: 403, Fig. 6) is transparent (Kwon: [0178]). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Kwon with the signal line layer comprising copper material, as taught by Chen, so as to improve device performance. Regarding claim 2, Kwon and Chen disclose the mark covering layer (Kwon: 350, Fig. 6) comprises a first surface facing away from the substrate (Kwon: 400, Fig. 6), and at least a portion of the first surface is inclined relative to a plane where the substrate (Kwon: 400, Fig. 6) is located. Regarding claim 5, Kwon and Chen disclose the first surface comprises a first portion and a second portion that are disposed side by side in a direction parallel to the plane where the substrate is located, the first portion is inclined relative to the plane where the substrate is located, and the second portion intersects the first portion (See Kwon Examiner Annotated Fig. 6 below). PNG media_image1.png 822 720 media_image1.png Greyscale Regarding claim 7, Kwon and Chen disclose a maximum height of the mark covering layer (Kwon: 403, Fig. 6) is not less than a height of the light-shielding layer (Kwon: 350, Fig. 6) in a thickness direction of the substrate (Kwon: 400, Fig. 6). Regarding claim 8, Kwon and Chen disclose the mark covering layer (Kwon: 403, Fig. 6) implicitly has a maximum height but do not disclose it is between 1 µm and 20 µm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select a maximum height of the mark covering layer to be between 1 µm and 20 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 9, Kwon and Chen disclose an orthographic projection of the mark covering layer (Kwon: 403, Fig. 6) on the substrate (Kwon: 400, Fig. 6) covers an orthographic projection of the alignment mark (Kwon: 350, Fig. 6) on the substrate. Regarding claim 10, Kwon and Chen disclose the mark covering layer (Kwon: 403, Fig. 6) at least partially exceeds the alignment mark (Kwon: 350, Fig. 6) in a first direction so that the mark covering layer (Kwon: 403, Fig. 6) covers a sidewall of the alignment mark (Kwon: 350, Fig. 6) in the first direction. Regarding claim 11, Kwon and Chen disclose a size of the mark covering layer (Kwon: 403, Fig. 6) is L1, a size of the alignment mark (Kwon: 350, Fig. 6) in a first direction is L2, and that L1 is greater than L2 since the mark cover layer covers a sidewall of the alignment mark in the first direction (see claim 10 rejection above). Yet, Kwon and Chen do not disclose L1 and L2 satisfy the relationship that L1≥ 1.2*L2. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select sizes of mark covering layer in a first direction (L1) and alignment mark in a first direction (L2) such that L1≥ 1.2*L2, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 12, Kwon and Chen disclose the mark covering layer (Kwon: 403, Fig. 6) is in contact with the alignment mark (Kwon: 350, Fig. 6). Regarding claim 15, Kwon discloses a display panel comprising an array substrate, wherein the array substrate comprising: A substrate (400, Fig. 6) ([0173]); An alignment mark (350, Fig. 6) disposed on a side of the substrate ([0175]); A mark covering layer (403, Fig. 6) disposed on a side of the alignment mark facing away from the substrate, wherein the mark covering layer (403, Fig. 6) at least partially overlaps the alignment mark (350, Fig. 6) ([0177]); and A signal line layer (630, Fig. 6), and the signal line layer (630, Fig. 6) is in contact with the mark covering layer (403, Fig. 6) and exposes at least a portion of the mark covering layer (403, Fig. 6) ([0179]). Yet, Kwon does not disclose the signal line layer is a light-shielding layer, wherein a transmittance of the light-shielding layer is less than a transmittance of the mark covering layer. However, Chen discloses a signal line layer may comprise copper ([0050]). Copper has the advantage of good electrical conductivity which would advantageously improve device performance. Teaching reference Mat discloses that copper is opaque (“Optical Properties”, pp 5) so the signal line layer of Kwon in view of Chen can be considered a “light-shielding layer” and the transmittance of the signal line layer or light-shielding layer can be considered to be less than a transmittance of the mark covering layer since the signal line layer or light-shielding layer is opaque, whereas the mark covering layer (Kwon: 403, Fig. 6) is transparent (Kwon: [0178]). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Kwon with the signal line layer comprising copper material, as taught by Chen, so as to improve device performance. Regarding claim 17, Kwon and Chen disclose the display panel according to claim 15 (see claim 15 rejection above) incorporated into a display device (Kwon: [0043]-[0044]). Allowable Subject Matter Claims 3-4, 6, 13-14, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to REEMA PATEL whose telephone number is (571)270-1436. The examiner can normally be reached M-F, 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /REEMA PATEL/Primary Examiner, Art Unit 2812 4/13/2026
Read full office action

Prosecution Timeline

Oct 16, 2023
Application Filed
Apr 28, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677516
DISPLAY DEVICE INCLUDING SELF-ALIGNED LEDS AND METHOD FOR MANUFACTURING DISPLAY DEVICE
3y 2m to grant Granted Jul 07, 2026
Patent 12677443
SELF-ALIGNED SUBSTRATE ISOLATION (SASI) OF GATE-ALL-AROUND NANOSHEET FIELD EFFECT TRANSISTORS
3y 4m to grant Granted Jul 07, 2026
Patent 12672522
SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME
3y 2m to grant Granted Jun 30, 2026
Patent 12672452
DISPLAY DEVICE
2y 6m to grant Granted Jun 30, 2026
Patent 12666716
CMOS STRUCTURE, AND FABRICATION METHODS OF FINFET CMOS, FD CMOS AND GAA CMOS
3y 3m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+6.4%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1122 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month