DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 26 February 2026. Claims 1-18 are pending in this application. Claims 12-18 are withdrawn from consideration, and Claims 1-11 are examined in this Office Action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 26 February 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6, 11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 6, Claim 6 depends from Claim 4 (and not claim 5). Claim 6 claims “a third dimension of the heavily doped region”. However, there is no antecedent basis for the limitation of “the heavily doped region” in the dependency chain of Claim 6. (Claims 1, 2, 4) There is a basis in Claim 5 (from which claim 6 does not depend) for “the heavily doped region”. For examination purposes, Claim 6 will be treated as depending from Claim 5 instead of Claim 4.
Regarding Claim 11, Claim 11 depends from Claim 10 (but not claim 2). Claim 11 claims “the third spacer comprise a dopant the same as that in the first spacer”. However, there is antecedent basis for dopant in the first spacer claimed in Claim 10, or Claim 1 from which claim 10 depends. There is a basis in Claim 2 for a dopant in the first spacer. For examination purposes, Claim 10 will be treated as depending from Claim 2 instead of Claim 1, so that Claim 11 includes Claim 2 in its dependency chain.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho et. al (US 9,548,366 B1) in view of over Lee (US 2006/0145253 A1).
Regarding Claim 1, Ho discloses (as shown in Fig. 15) A semiconductor device ([Col. 4 Lines 64-66] In an embodiment, the gate stacks 28 and the source/drain regions 30 may form transistors, such as metal-oxide-semiconductor FETs (MOSFETs)), comprising:
a substrate ([Col. 2 Line 67] substrate 20);
a plurality of first gate electrodes ([Col. 6 Line 29] gate electrodes 40) (See An. Fig. 15; Plurality of First Gate Electrodes) on the substrate (20); (See Fig. 15, showing the gate electrodes 40 are formed on the substrate 20)
a first spacer ([Col. 5 Line 6] Gate spacers 26) disposed on a sidewall of each of the plurality of first gate electrodes (40); ([Col. 5 Lines 6-7] Gate spacers 26 are formed on opposite sides of the gate stacks 28)
a first lightly doped region ([Col. 5 Lines 22-24] In another embodiment, the source/drain regions 30 may include a lightly doped region (sometimes referred to as a LDD region) and a heavily doped region) disposed within the substrate and between two of the plurality of first gate electrodes;
and a plurality of second gate electrodes ([Col. 6 Line 29] gate electrodes 40) (See An. Fig. 15; Plurality of Second Gate Electrodes),
wherein the plurality of first gate electrodes (40, An. Fig. 15; Plurality of First Gate Electrodes) has a first distance, and the plurality of second gate electrodes (40, An. Fig. 15; Plurality of Second Gate Electrodes) has a second distance different from the first distance; ([Col. 9 Lines 5-8] the opening 58B is not self-aligned as the pitch between the gate stack 42B and the nearest gate stack 42A is larger than the pitch of the gate stacks 42A )
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However, Ho fails to disclose a second lightly doped region disposed within the substrate (20) and between two of the plurality of first gate electrodes (40);
wherein the first lightly doped region overlaps the second lightly doped region,
the first lightly doped region has a first dimension,
and the second lightly doped region has a second dimension less than the first dimension along a first direction.
Lee discloses (as shown in Fig. 3G) a second lightly doped region ([0032] a second LDD area 40b) disposed within the substrate ([0029] substrate 10) and between two of the plurality of first gate electrodes ([0030] polysilicon gate 30), ([0032] Next, as shown in FIG. 3C, a second LDD implant process in which the impurity ions are implanted and thermally annealed using the polysilicon gate 30 and the first spacer 32a as a mask.)
wherein the first lightly doped region ([0030] first LDD area 40a) overlaps the second lightly doped region (40b), (See Figs. 3B-C, showing the second LDD area 40b is formed to overlap with the first LDD area 40a)
the first lightly doped region (40a) has a first dimension, and the second lightly doped region (40b) has a second dimension less than the first dimension along a first direction. (See Fig. 3G, showing the second LDD area 40b has a smaller width than the first LDD area 40a)
Lee teaches that the second LDD area 40b prevents the diffusion of impurities towards the lower portion of the gate 30. ([0036] According to an exemplary embodiment of the present invention, a double LDD structure is formed in a MOS transistor such that a lateral diffusion of impurities towards the lower portion of a gate can be effectively prevented when an LDD is formed.) Therefore, it would have been obvious to replace the single LDD are of Ho with the double LDD area of the embodiment of Lee in order to prevent the diffusion of impurities towards the lower portion of the gate.
Regarding Claim 10, Ho further discloses (as shown in Fig. 16) a third spacer ([Col. 5 Line 6] Gate spacers 26) disposed on a sidewall of each of the plurality of second gate electrodes (40). (See An. Fig 15, showing the gate spacers 26 are also on the sidewalls of the plurality of second gate electrodes)
Claim(s) 2, 4-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho in view of Lee as applied to claim 1 above, and further in view of Wu et. al (US 2020/0135887 A1)
Regarding Claim 2, Ho further discloses (as shown in Fig. 2, 16) a second spacer ([Col. 5 Line 49] etch stop layer 32) covering the first spacer (26) ([Col. Lines 49-53] FIG. 2 illustrates the formation of an etch stop layer 32 over the substrate 20, the gate stacks 28, the gate spacers 26, and the source/drain regions 30. The etch stop layer 32 may be conformally deposited over components on the substrate 20.)
However, Ho fails to disclose wherein the first spacer (26) comprises a dopant.
Wu discloses (as shown in Fig. 17) wherein the first spacer ([0031] The remaining portions 311 of the first spacer layer 310 on sidewalls of the dummy gate stack 106 can be interchangeably referred to inner spacers 311) comprises dopants ([0078] a concentration of the k-value reduction impurities in the inner spacer is greater than a concentration of the k-value reduction impurities in the outer spacer)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the application to combine the teachings of Lee and Wu. Wu teaches that by including dopants in the sidewall spacers, the spacers have reduced dielectric constants compared to the un-doped spacers, which reduces the parasitic capacitance, improving the resistance capacitance delay. ([0075] One advantage is that the doped gate spacer has a reduced dielectric constant as compared to the un-doped gate spacer, which in turn will reduce the parasitic capacitance and thus improve the resistance capacitance (RC) delay.) Therefore, it would have been obvious to include dopants in the inner spacers in order to reduce parasitic capacitance.
Regarding Claim 4, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have a material of the second spacer (32) is the same as that of the first spacer (26) based on the teaching of Ho. Ho teaches that the gate spacer 26 is made from SiN, oxynitride, SiC, SiON, oxide, combinations thereof ([Col. 5 Lines 12-13]). Ho further teaches that the etch stop layer is 32 may be silicon nitride, silicon carbide, silicon oxide, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, the like, or a combination thereof ([Col. 5 Lines 53-57]). Since both the gate spacer 26 and the etch stop layer 32 can be made from silicon nitride, silicon carbide, silicon oxide, and low-k dielectrics such as carbon doped oxides, it would have been obvious to make them from the same material.
Regarding Claim 5, Ho further discloses a heavily doped region disposed within the substrate and overlaps the first lightly doped region. ([Col.5 Lines 22-34] In another embodiment, the source/drain regions 30 may include a lightly doped region (sometimes referred to as a LDD region) and a heavily doped region… After the gate spacers 26 are formed, the source/drain regions 30 may then be heavily doped with an implantation process using the gate stacks 28 and gate spacers 26 as masks… The lightly doped regions are primarily underneath the gate spacers 26 while the heavily doped regions are outside of the gate spacers along the substrate 20.)
However, Ho fails to disclose the heavily doped region overlaps the second lightly doped region.
Lee further discloses (as shown in Fig. 3G) the heavily doped region ([0033] a source-drain diffusion area 40c with a high concentration.) overlaps the second lightly doped region (40b). (See Fig. 3G, showing the source-drain diffusion region 40c overlaps the second LDD region 40b)
Regarding Claim 6, Lee further discloses (as shown in Fig. 3G) wherein a third dimension of the heavily doped region (40c) is less than the second dimension of the second lightly doped (40b) region along the first direction. (See fig. 3G, showing the second LDD region 40b extends further than the source-drain diffusion region 40c in the horizontal direction)
Regarding Claim 7, Ho further discloses (as shown in Fig. 15) a conductive via ([Col. 9 Line 64] the conductive layer 60) connected to the heavily doped region, ([Col. 9 Lines 64-66] the conductive layer 60 in the openings 58A and 58B contacts the expose surfaces of the source/drain regions 30)
wherein the conductive via (60) is in contact with the second spacer (32). (See An. Fig. 15, showing the conductive via 60A1 in contact with the etch stop layer 32 in the plurality of first gate electrodes)
Regarding Claim 8, Ho further discloses (as shown in Fig. 15) a spacer protection layer ([Col. 5 Line 60] an interlayer dielectric (ILD) 34) covering the first spacer (26) and the second spacer (32). (Col. 5 Lines 60-61] In FIG. 3, an interlayer dielectric (ILD) 34 is deposited over the structure illustrated in 2) (See Fig. 15)
Regarding Claim 9, Ho further discloses (as shown in Fig. 15) a conductive via ([Col. 9 Line 64] the conductive layer 60) connected to the heavily doped region ([Col. 9 Lines 64-66] the conductive layer 60 in the openings 58A and 58B contacts the expose surfaces of the source/drain regions 30),
wherein the conductive via (60) is separated from the second spacer (32) by the spacer protection layer (34). (See An. Fig. 15, showing the conductive via 60B separated from the etch stop layer 32 in the horizontal direction in the plurality of second gate electrodes.)
Claim Interpretation Note: The first and second plurality of gate electrodes in Claim 1 can be swapped, i.e. the plurality of second gate electrodes in An. Fig. 15 of Ho can be the plurality of first gate electrodes in Claim 1, and the plurality of first gate electrodes in An. Fig. 15 of Ho can be the plurality of second gate electrodes in Claim 1. This allows the plurality of second gate electrodes in Claim 1 to include the not self-aligned contacts with the ILD layer 34.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the conductive via (60) is separated from the second spacer (32) on surface of the source/drain region (30). Lee teaches the second spacer (32b) is used as a mask for an ion implantation of the heavily doped region (40c). ([0033] The second spacer 32b functions as a mask when the source-drain diffusion area is formed in the ion implantation process) Therefore, it would have been obvious to remove the portions of the etch stop layer (32) on the portion of the heavily doped source/drain region in order to form the heavily doped source/drain region. This would cause the conductive via (60B) to be separated from the etch stop layer (32) on the surface of the source/drain region (30)
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho in view of Lee as applied to claim 10 above, and further in view of Wu et. al (US 2020/0135887 A1)
Regarding Claim 11, Wu further teaches (as shown in Fig. 14a) wherein the third spacer ([0025] inner spacers 312) comprise a dopant the same as that in the first spacer ([0031] inner spacers 311). (See Fig. 14A, showing the same dopant being introduced into both the inner spacers 311 and 312)
Allowable Subject Matter
Allowable Subject Matter
Claim 3 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, Ho in view of Lee and Wu fails to disclose wherein the dopant of the first spacer is the same as that of the second lightly doped region.
Since the Claim contains a limitation not found in the prior art, it contains allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893