DETAILED ACTION
Claims 1-14 and 16-18 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. At this point in time, the examiner recommends --Software-Directed Inhibiting of Branch Prediction based on Length of Stable Path of Instructions--.
The abstract of the disclosure is objected to because of the following minor informalities:
In line 4, there is a lack of basis for “The instructions when executed”. Please amend to clarify whether applicant is referring to the instructions in line 2 or line 3. The examiner recommends inserting a descriptor such as “specific” after “having” in line 2, and then again before “instructions” in line 4.
In line 5, “The instructions” similarly lacks basis. Does applicant mean --The program code”? Please amend for improved clarity/readability.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections/Recommendations
In claim 1, line 8, the examiner recommends inserting --executable-- before “computer”.
Claim 1 is objected to because of the following informalities:
In line 12, it appears that “persisting” should be deleted for improved grammar. To the examiner, “inhibit operation…through execution…” reads more correctly than “inhibit operation…persisting through execution…”.
In claim 4, line 2, the examiner recommends inserting --computer-- after “executable”.
In claim 4, line 3, the examiner recommends inserting --executable computer-- before “program”.
Claim 6 is objected to because of the following informalities:
In lines 1-2, please reword to avoid the interpretation that the processor is operatively coupled to a branch prediction unit (which is not the case based on FIG.1 (the processor includes the branch prediction unit)). The examiner recommends rewording as either (1) --A computer apparatus comprising a branch prediction unit and a processor operatively coupled to memory, the apparatus configured to:--, or (2) A computer apparatus comprising a processor operatively coupled to memory and comprising a branch prediction unit, the apparatus configured to:--.
In lines 7-8, there is a lack of basis for “the stable path approaching execution”. The examiner recommends rewording to --prior to executing the stable path, read, in the computer program code, an indicator indicating a length of the stable path,…--.
In the 2nd to last paragraph, it appears that “persisting” should be deleted for improved grammar.
Claim 7 is objected to because of the following informalities:
In line 1, replace “is” with --indicators--.
Claim 10 is objected to because of the following informalities:
In line 2, delete “also”.
In line 2, it appears that “for” should be replaced with --to--.
Claim 11 is objected to because of the following informalities:
In lines 2-3, there is a lack of basis for “said inhibiting operation”, which can refer to the inhibiting of line 1 or to that in claim 6. The examiner recommends inserting --said-- before “inhibiting” in claim 6, line 1.
Claim 16 is objected to because of the following informalities:
Insert --and-- at the end of line 5.
In lines 6-7, there is a lack of basis for “the stable path approaching execution”. The examiner recommends rewording to --an indicator preceding the stable path and indicating a length of the stable path,…--.
In the last paragraph, there is a lack of basis for “the branch prediction unit”. Please replace “the” with --a--.
In the 2nd to last line, it appears that “persisting” should be deleted for improved grammar.
In the 2nd to last line, replace “cease” with --ceases--.
Claim 17 is objected to because of the following informalities:
It appears that applicant’s intention is to claim a method; however, applicant is not claiming method steps. Instead, applicant is claiming a computer configured in a particular manner. The examiner recommends rewording lines 1-2 to --A method performed by a computer including a processor operatively coupled to memory, the method comprising:--.
Should applicant disagree with the previous objection, the claim is also grammatically incorrect (“computer configured to: generating…and storing”).
In the 2nd to last paragraph, it appears that “persisting” should be deleted for improved grammar.
In claim 17, line 8, the examiner recommends inserting --executable-- before “computer”.
Claim 18 is objected to because of the following informalities:
Lines 1-2 are grammatically incorrect. The examiner recommends rewording to
--A method performed by a computer having a branch prediction unit, the method comprising:--.
In lines 7-8, there is a lack of basis for “the stable path approaching execution”. The examiner recommends rewording to --prior to executing the stable path, reading, in the computer program code, an indicator indicating a length of the stable path,…--.
In the last paragraph, it appears that “persisting” should be deleted for improved grammar.
In the 2nd to last line, replace “cease” with --ceasing--.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claim 16, a computer apparatus reading the indicator, executing the program code, inhibiting operation of the branch prediction unit, and ceasing inhibition”. From FIG.1, the apparatus is interpreted as a processor. The examiner recommends replacing the claimed “computer apparatus” with --processor-- to avoid 112(f) interpretation.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-5 and 17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more.
Regarding step 1 of the subject matter eligibility test (MPEP 2106), claims 1-5 are to a machine, and claim 17 is to a process.
Regarding claim 1:
Considering step 2A (prong 1) of the test, the claim recites multiple aspects related to generating executable program code including the claimed arranging and indicator inclusion, This generation constitutes an abstract idea that falls into the category of mental processes (MPEP 2106.04(a) and (a)(2)(III)). Generating code can be done by a human using pen and paper. This could involve observing, evaluating, or judging that code includes a stable path and providing the claimed indication therefor. It could also involve writing/arranging code in such a way to maximize the length of a stable path, e.g. by reducing conditional branches where possible.
Considering step 2A (prong 2) of the test, the claim recites additional elements of:
a computer apparatus comprising a processor operatively coupled to memory, the apparatus configured to perform the generating, arranging, and indicator inclusion by the processor; and
storing, by the processor, the generated code for subsequent use.
The processor and memory are generic computer components used as a tool to perform the abstract idea. The storing of code is insignificant post-solution activity that is incidental to the primary abstract idea and is a mere nominal addition to the claim. The courts have identified such generic components and activity as not integrating the abstract idea into a practical application (MPEP 2106.04(d)(I)).
Considering step 2B of the test, and considering the additional elements both individually and in combination, the courts have identified that the generic components to perform the abstract idea also do not amount to significantly more (MPEP 2106.05(I)(A)). Furthermore, the courts have determined that storing data to memory is well-understood, routine, and conventional activity that does not amount to significantly more (MPEP 2106.05(I)(A) and 2106.05(d)(II)(iv)).
Thus, claim 1 is not patent-eligible under 101.
Regarding claim 2, there claim merely sets forth an aspect of the mental process of the arranging/generating so as to take into account a threshold probability. Since claim 2 includes no additional element, the mental process is not integrated into an application, and there is not significantly more.
Regarding claim 3, there claim merely sets forth an aspect of the mental process of the arranging/generating so as to insert a specific type of instruction in the code. Since claim 3 includes no additional element, the mental process is not integrated into an application, and there is not significantly more.
Regarding claim 4, the generating, analyzing, and adjusting are part of a mental process, where a human can analyze stable paths and adjust ordering of instructions to generate different versions of code to try to find an ideal version for execution. The additional element of executing the code is insignificant post-solution activity that is incidental to the abstract idea. Execution of code is also well-understood, routine, and conventional and, thus, does not integrate the abstract idea into a practical application, nor amount to significantly more.
Regarding claim 5, the claimed determine is part of a mental process. There are no further additional elements claimed. Therefore, claim 5 does not set forth a limitation that integrates the abstract idea into a practical application, or amounts to significantly more.
Claims 17 is not patent-eligible under 101 for similar reasons as claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 6, 16, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gray et al. (US 20160378492 A1).
Regarding claim 6, Gray has taught a computer apparatus comprising a processor operatively coupled to memory and a branch prediction unit (Figure 1 and [0024]: "Processor 100 may include an instruction cache 104 a branch predictor 106"), the apparatus configured to:
execute computer program code stored in memory and having a stable path which consists essentially of a plurality of instructions expected to be executed in a sequence ([0012]: processors "may have instructions organized in groups, e.g., instruction blocks, that are fetched, executed, and committed atomically" and "instructions inside a group may execute in a data flow order"; In other words, the group of instructions is the stable path, which executes in data flow order, i.e. sequentially), the plurality of instructions occurring in the stable path contiguously according to the sequence (Table 3 with [0016] shows types of information (fields) included in a group header including a SIZE field which indicates a group header followed by an encoded SIZE number of instructions in the group; In other words, the group of instructions, i.e., stable path, follow the group header contiguously);
read, in the computer program code, an indicator corresponding to the stable path approaching execution and indicating a length of the stable path, the indicator included in the computer program code during generation thereof ([0015] "Each group of instructions may have certain information associated with the group of instructions, such as control information and/or meta-information related to the group of instructions. This information may be generated by the compiler during compilation of higher-level code, such as C or C++ into instructions for execution on a processor" and such information is "provided to the processor using a group header"; in other words the group header, i.e. indicator, is read and corresponds to the group of instructions, i.e. stable path, approaching execution. Also, Table 3 with [0016] shows that SIZE field indicates a group header followed by an encoded SIZE number of instructions in the group); and
in response to reading the indicator, inhibit operation of the branch prediction unit persisting through at least one subsequent execution of the stable path and cease inhibition following execution of the stable path based on the length of the stable path (Table 3 with [0016]: The XFLAGS field in the group header "may include flags that indicate special execution requirements for the group of instructions" and "XFLAGS[1] Inhibit Branch Predictor" is described as a "flag when set may result in the branch predictor being inhibited". Specifically, Table 3 with [0016] "XFLAGS[1] when set may result in the branch predictor being inhibited"; In other words, branch prediction is inhibited while the group of instructions, i.e. stable path, is being executed. Once the group is done executing, the branch predictor resumes normal operation, i.e. inhibition is ceased, at some point following execution of the stable path).
Claims 16 and 18 are rejected for similar reasons as claim 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2004/0181654) in view of the examiner’s taking of Official Notice and Fujii (US 2018/0136917).
Referring to claim 1, Chen has taught a computer apparatus comprising a processor (from paragraph 40, a compiler is software that is executed by a processor), the apparatus configured to:
generate, by the processor, executable computer program code having a stable path which consists essentially of a plurality of instructions expected to be executed in a sequence, the plurality of instructions occurring in the stable path contiguously according to the sequence (e.g. a processor executing the compiler will generate the code of TABLE 2 in paragraph 29, where a stable path would comprise instructions 4a, 5a, and 6a. These three instructions do not comprise a branch and thus are expected to execute in sequence);
the generating of the executable computer program code comprising including, by the processor, an indicator therein to inhibit operation of a branch prediction unit of the processor persisting through execution of the stable path and cease inhibition following execution of the stable path based on a length of the stable path (based on the description in paragraphs 28 and 40, a compiler sets individual branch prediction enabling information (FIG.3, field 120) in each instruction. This information, in a current instruction, either enables or inhibits branch prediction for the next instruction. In Table 2, the claimed indicator is mapped to the collection of branch prediction enabling information for instructions 3a, 4a, 5a, and 6a. This indicator inhibits branch prediction for the entirety of the stable path. When the stable path is ended, the enable indicator for instruction 6a will enable prediction for the first instruction following the stable path (Bra_2a));
Chen has not taught that the processor is operatively coupled to memory. However, Official Notice is taken that coupling a processor to an external memory such as RAM was well known in the art before applicant’s invention. RAM is cheaper and slower that on-chip memory; however, the capacity is much greater, thereby providing a space to store large amounts of data for relatively cheap. RAM is a foundational component of a known memory hierarchy, which involves various levels of memory to balance cost, capacity, and speed of storage. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that the processor is operatively coupled to memory.
Chen has also not taught the generating of the executable computer program code comprising arranging, by the processor, the computer program code to maximize a length of the stable path while respecting one or more conditions or constraints. However, Fujii has taught a compiler than can profile code so as to make optimizations include removing conditional branches that always evaluate to true, for instance (see paragraph 72). This amounts to respecting the condition of the branch (e.g. if it is determined to always be taken, then the code is arranged in a way that maintains that condition). As applied to Chen, one of ordinary skill in the art would have recognized that, if branches are detected as always evaluating to true, then not only can they be removed, leaving more consecutive non-branch instructions, but the branch prediction could be disabled longer. For instance, in TABLE 2, if it is determined that instruction Bra_2a always evaluates to true, the compiler can remove that instruction (and it’s fall-through instruction Ins_8a). With this change, Ins_6a’s indicator can be changed to “Disable” because it no longer needs to enable prediction for the next instruction. This means, the length of the stable path would be maximized in this example and would include instructions 4a, 5a, 6a, and 9a. In other words, the compiler would arrange the code to include fewer branches where possible, extend the stable path length, and enable the branch predictor less often, thereby saving even more power. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that the generating of the executable computer program code compris[es] arranging, by the processor, the computer program code to maximize a length of the stable path while respecting one or more conditions or constraints.
Finally, Chen, as modified, has not taught that the apparatus is configured to store, by the processor, the generated executable computer program code for subsequent use. In short, Chen does not disclose that the same apparatus both compiles and executes the compiled code. However, Official Notice is taken that such was well known in the art before applicant’s invention. Compiling code and executing the compiled code with the same hardware allows for quick debugging and changes to the code to be effected, while also minimizing the number of processors needed. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that the compiler is executed by the processor of Chen. Overall, the processor of Chen will compile the code, which will eventually be stored in memory for fetching by the processor for execution.
Referring to claim 2, Chen, as modified, has taught the apparatus of claim 1, wherein the one or more constraints or conditions include maintaining at least a threshold probability that the plurality of instructions will be executed in sequence (the instructions that form the stable path prior to arrangement are all non-conditional, i.e., they are not branch instructions. Thus, they are expected to execute in sequence with N% probability. Upon arrangement, including removal of a branch, the extended stable path is still expected to execute in sequence with N% probability because the instructions are again all non-conditional. This is the reason why the stable path length can be extended, because the expected probability of execution is sequence remains at N%).
Referring to claim 3, Chen, as modified, has taught the apparatus of claim 1, wherein the indicator is a specialized branch instruction which leads to the stable path, a marker instruction (instruction 3a is a “marker” instruction), an instruction included in the computer program code along with but separate from a branch instruction which leads to the stable path, or an instruction which precedes the stable path by a fixed number of instructions and which indicates a start of the stable path (instruction 3a is an instruction which precedes the stable path by one instruction).
Referring to claim 4, Chen, as modified, has taught the apparatus of claim 1, wherein the arranging comprises generating, executing and analyzing candidate versions of the executable program code, and adjusting the candidate versions of the program code to arrive at the generated executable program code based on the analyzing (again, see Fujii, paragraph 72).
Referring to claim 5, Chen, as modified, has taught the apparatus of claim 4, wherein the analyzing comprises determining an indication of probability that the plurality of instructions will be executed in sequence (the compiler, via profiling the code in Fujii, determines that the branch is taken 100% of the time (it is determined to always result in meeting its branch condition). This translates to a probability that the target of the branch (e.g. instruction 9a in Chen) will be executed in sequence with instructions 4a, 5a, and 6a, 100% of the time).
Claim 17 is rejected for similar reasoning as claim 1.
Claims 6-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of the examiner’s taking of Official Notice and Schuler et al. (US 2008/0082843) (as previously cited).
Referring to claim 6, Chen has taught a computer apparatus comprising a processor (FIG.2, 1000) and a branch prediction unit (FIG.2, 1120), the apparatus configured to:
execute computer program code stored in memory (from paragraph 38, “Programs using the present invention method can be distributed in a normal matter by way of magnetic or optical media (or via a network connection), loaded into memory and executed by the CPU 1000”) and having a stable path which consists essentially of a plurality of instructions expected to be executed in a sequence, the plurality of instructions occurring in the stable path contiguously according to the sequence (e.g. the code of TABLE 2 in paragraph 29 includes a stable path having at least instructions 4a, 5a, and 6a. These three instructions do not comprise a branch and thus are expected to execute in sequence);
Chen has not taught that the processor is operatively coupled to memory (Chen instead only shows an instruction cache memory being part of the processor (FIG.2)). However, Official Notice is taken that coupling a processor to an external memory such as RAM was well known in the art before applicant’s invention. RAM is cheaper and slower that on-chip memory; however, the capacity is much greater, thereby providing a space to store large amounts of data for relatively cheap. RAM is a foundational component of a known memory hierarchy, which involves various levels of memory to balance cost, capacity, and speed of storage. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that the processor is operatively coupled to memory.
Chen has not taught that the apparatus is configured to read, in the computer program code, an indicator corresponding to the stable path approaching execution and indicating a length of the stable path, the indicator included in the computer program code during generation thereof. Instead, Chen has taught that each instruction includes a bit that is set to enable or disable branch prediction for the next instruction (FIG.3, paragraph 28, TABLEs 1-2, etc.). However, Schuler has analogously taught disabling the predictor for non-branch instructions, but does so by encoding a count value for a number of non-branch instructions to be fetched (e.g. see paragraphs 53-54). This value is stored in a counter, which is decremented upon each fetch. When the counter expires (e.g. reaches 0), the next instruction expected is a branch and so the predictor is enabled. One of ordinary skill in the art would have recognized that one could’ve have substituted Schuler’s encoding for Chen’s and achieved the same results. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen to include Schuler’s encoding instead of its own. For instance, taking TABLE 2 as an example, instead of instructions 3a, 4a, 5a, and 6a each including a bit indicator, instruction 3a could be modified to include a field having a disable length. In this example the field could be set to a length of 3, which would indicate to disable the predictor for the next three instructions. This length of 3 provides the same information as Chen’s indicator bits.
Chen, as modified, has taught in response to reading the indicator, inhibit operation of the branch prediction unit persisting through at least one subsequent execution of the stable path and cease inhibition following execution of the stable path based on the length of the stable path (see the example given above).
Referring to claim 7, Chen, as modified, has taught the apparatus of claim 6, wherein the indicator is that the stable path is about to be executed or is predicted to be executed (again, in Chen, as modified, instruction 3a would include a length indicator of 3, which means the stable path starts with the next instruction and includes three instructions).
Referring to claim 8, Chen, as modified, has taught the apparatus of claim 6, wherein the indicator is associated with a branch instruction leading to the stable path (from TABLE 2, the indicator would be part of instruction 3a, which immediately follows the branch Bra_1a. The indicator can be said to be associated with that preceding branch which leads to the stable path).
Referring to claim 9, Chen, as modified, has taught the apparatus of claim 6, wherein the indicator is associated with a start of the stable path (as described above, instruction 3a includes the indicator which is associated with the start of the stable path at instruction 4a).
Referring to claim 10, Chen, as modified, has taught the apparatus of claim 6, wherein inhibiting operation of the branch prediction unit comprises storing data in a data structure which is also used for support operation of the branch prediction unit (FIG.2, latch 1121, which would implement the wake counter of Schuler to store and decrement the count), the stored data used in triggering said inhibiting operation of the branch prediction unit during at least one subsequent execution of the stable path (the latch stored enable/disable information used to trigger the inhibiting for the stable path).
Referring to claim 11, Chen, as modified, has taught the apparatus of claim 6, wherein inhibiting operation of the branch prediction unit comprises storing data in a data structure which is dedicated for use in triggering said inhibiting operation of the branch prediction unit during at least one subsequent execution of the stable path (again, see latch 1121 of Chen. This is a dedicated structure that controls enabling/disabling of the prediction. As modified, the latch would be implemented as a counter (like the wake counter in Schuler)).
Referring to claim 12, Chen, as modified, has taught the apparatus of claim 6, but has not taught wherein the indicator is included in the computer program code as a specialized branch instruction which leads to the stable path. However, this is merely due to the example given in TABLE 2. In the same TABLE, a branch instruction Bra_2a includes enable/disable information for a subsequent instruction. One of ordinary skill in the art would have recognized that instructions 4a, 5a, and 6a could have instead been at label_2a such that Bra_2a is a specialize branch that would include the indicator for the stable path. Another implementation could include instruction 4a being at some label_X and some branch somewhere else in the program would branch to label_X, which means the branch would be a specialized branch that would include the indicator for the stable path. Such would allow the stable path to be reached as a result of a branch, either conditional or unconditional. Generally, such modifications are based on the program itself and the needs of the programmer. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that the indicator is included in the computer program code as a specialized branch instruction which leads to the stable path.
Referring to claim 13, Chen, as modified, has taught the apparatus of claim 6, wherein the indicator is included in the computer program code along with but separate from a branch instruction which leads to the stable path (see TABLE 2, and note instruction 3a, which would include the indicator for the stable path. This indicator is provided along with but separate from branch Bra_1a, which leads to the stable path).
Referring to claim 14, Chen, as modified, has taught the apparatus of claim 6, wherein the indicator is included in the computer program code as an instruction which precedes the stable path by a fixed number of instructions and which indicates a start of the stable path (instruction Ins_3a precedes the stable path by one instruction. This is fixed in the design, where each instruction indicates for the next. This instruction, as modified, will include the length, which indicates that the next instruction is the start of the path followed by N more instructions that make up the length).
Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Schuler.
Claim 16 is rejected for a subset of reasoning set forth in the rejection of claim 6 (note that the processor operatively coupled to memory is not required). Further, Chen has taught a non-transitory computer readable medium having stored thereon computer program code (from paragraph 38, “Programs using the present invention method can be distributed in a normal matter by way of magnetic or optical media (or via a network connection), loaded into memory and executed by the CPU 1000”).
Claim 18 is rejected for a subset of reasoning set forth in the rejection of claim 6 (again note that the processor operatively coupled to memory is not required).
Response to Arguments
On page 9 of applicant’s response, applicant argues that claim 1 has been amended such that the operations are performed by a processor and, thus, the 101 rejection should be withdrawn.
The examiner notes the amendment. However, the 101 rejection is maintained because a processor is a generic computer component that is performing the abstract idea. The courts have determined such to not integrate the abstract idea into a practical application, and to not amount to significantly more.
On page 9 of the response, applicant further argues that the indicator is claimed to inhibit operation of a branch prediction unit of a processor and, thus, the 101 rejection should be withdrawn.
The examiner notes the distinction between performing inhibiting of the predictor, and merely providing an indication that indicates to inhibit the predictor. Those claims that actually perform inhibition have not been rejected under 101. However, a human can generate code that includes an indication to inhibit without the inhibiting needing to occur as part of the generation. The examiner recommends claiming that the apparatus is configured to inhibit the predictor in response to reading the indicator.
On pages 9-10, applicant argues that the code is stored, by the processor, for subsequent use by the processor and that this, and the preceding steps, cannot be performed in the mind.
Only the generating, arranging, and including in claim 1 are part of the mental process. A processor claimed to perform these is not enough to integrate or amount to significantly more. Further, the storing is not a mental process but extra-solution activity, which is also not enough, per the courts, to satisfy 101.
The first full paragraph on page 10 is not persuasive for similar reasoning given above.
On page 10 of the response, applicant argues that the claimed operations improve the functioning of a computer and thus there is practical application.
The examiner notes that the generating may improve the computer; however, the generating is part of the mental process and the improvement cannot come solely from the mental process (from MPEP 2106.05(a), “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements.”). The only additional elements are processor, memory, and storing, which do not provide an improvement. These are generic components and/or extra-solution activity.
On page 10 of the response, applicant argues that the steps are not performed in isolation but with hardware to inhibit a branch prediction unit.
As stated above, no inhibition is required by claim 1. Only generating an indication that indicates to inhibit is required. This is a mental process.
Applicant argues on pages 11-12 that Chen does not teach claim 6 as amended.
The examiner agrees. However, the examiner asserts that it is obvious to modify Check to render claim 6 unpatentable.
On page 12 of the response, applicant argues that Gray uses markers for decoding and issuing, not for inhibiting branch prediction unit. Applicant also argues that SIZE is not used for branch prediction inhibition.
The examiner respectfully disagrees. SIZE + XFLAGs is the indicator. These two combined specify the branch prediction is disabled for the amount of instructions in the group.
On page 13 of the response, applicant argues that claim 1 requires inserting an indicator that specifies path length.
The examiner respectfully disagrees. Claim 6 requires such an indicator. However, claim 1’s indicator does not necessarily have to specify the length.
All remaining arguments are moot since the examiner is no longer using the secondary references argued.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chiao (2007/0130450) has taught disabling a branch predictor for a time period corresponding to a distance between two branches.
Blasco (2015/0169041) has taught disabling a branch predictor when a next fetch group is determined to not include a conditional branch instruction.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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