Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II in the reply filed on 3/4/2026 is acknowledged.
Claim 7 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected species I, III-IV claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 19 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by US 20180102313 A1 (Shih).
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Regarding claim 19, Shih shows (Fig. 12) a semiconductor package, comprising:
a redistribution substrate (410, para 45) having an upper surface and a lower surface, opposite to each other, and including a plurality of redistribution layers (414,419 para 24) spaced apart between the upper and lower surfaces;
a semiconductor chip (11,12, para 45) disposed on the upper surface of the redistribution substrate, and electrically connected to the redistribution layers;
an upper encapsulant (560, para 46) encapsulating at least a portion of the semiconductor chip and disposed on the upper surface of the redistribution substrate;
a plurality of passive components (612, 613, para 37) and a plurality of bumps (810, para 44) disposed on the lower surface of the redistribution substrate and electrically connected to the redistribution layers; and
a lower encapsulant (550, para 47) covering side surfaces of the plurality of passive components and side surfaces of the plurality of bumps and disposed on the lower surface of the redistribution substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 1-3,8,10,12,15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of US 20200168536 A1 (Link).
Regarding claim 1, Shih shows (Fig. 12) a semiconductor package, comprising:
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a redistribution substrate (410, para 45) having an upper surface and a lower surface, opposite to each other, and including a plurality of redistribution layers (414,419 para 24) spaced apart between the upper and lower surfaces;
a semiconductor chip (11,12, para 45) disposed on the upper surface of the redistribution substrate, and electrically connected to at least one of the plurality of redistribution layers;
an upper encapsulant (560, para 46) encapsulating at least a portion of the semiconductor chip and disposed on the upper surface of the redistribution substrate;
a passive component (613, para 37) disposed on the lower surface of the redistribution substrate, and electrically connected to at least one of the plurality of redistribution layers;
a lower encapsulant (550, para 47) encapsulating at least a portion of the passive component and disposed on the lower surface of the redistribution substrate, and having a plurality of openings (for vias 510, para 39) exposing lowermost redistribution layers among the plurality of redistribution layers;
a plurality of bumps (810, para 43).
Shih does not show a plurality of bumps respectively disposed within the plurality of openings, each of the plurality of bumps respectively including a first portion in electrical contact with a lowermost redistribution layer and a second portion below the first portion, the second portion including an outer portion protruding downwardly below its respective opening.
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Link shows (Fig. 1) a plurality of bumps (116, para 21) respectively disposed within the plurality of openings (openings made for bumps), each of the plurality of bumps respectively including a first portion (116 above A-A’) in electrical contact with a lowermost redistribution layer (164, para 20) and a second portion (116 below A-A’) below the first portion, the second portion including an outer portion (116 below 114 bottom line) protruding downwardly below its respective opening.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Link, with plurality of bumps, to the invention of Shih.
The motivation to do so is that the selection of an art recognized bumps of Link is suitable for the intended use of Shih (MPEP §2144.07).
Regarding claim 2, Shih as previously modified with Link shows wherein within the plurality of openings, a width of the first portion of a bump is smaller than a width of the second portion of the bump (a shown above in Link).
Regarding claim 3, Shih as previously modified with Link shows wherein at least one of the first portion of a bump and the second portion of the bump is in contact with an inner wall of its respective opening.
Regarding claim 8, Shih as previously modified with Link shows wherein the first portion and the second portion of each of the plurality of bumps are integrally connected.
Regarding claim 10, Shih as previously modified with Link shows wherein the lower encapsulant (550, para 47) covers an entire side surface of the passive component (613, para 37).
Regarding claim 12, Shih shows (Fig. 12) wherein the semiconductor chip comprises a first semiconductor chip (11) and a second semiconductor chip (12) electrically connected to each other through the redistribution substrate (para 45).
Regarding claim 15, Shih shows (Fig. 12) a semiconductor package, comprising:
a redistribution substrate (410, para 45) having an upper surface and a lower surface, opposite to each other, and including a plurality of redistribution layers (414,419 para 24) spaced apart between the upper and lower surfaces;
a semiconductor chip (11,12, para 45) disposed on the upper surface of the redistribution substrate, and electrically connected to at least one of the plurality of redistribution layers;
an upper encapsulant (560, para 46) encapsulating at least a portion of the semiconductor chip and disposed on the upper surface of the redistribution substrate;
a passive component (613, para 37) disposed on the lower surface of the redistribution substrate, and electrically connected to at least one of the plurality of redistribution layers;
a lower encapsulant (550, para 47) encapsulating at least a portion of the passive component and disposed on the lower surface of the redistribution substrate, and having a plurality of openings (for vias 510, para 39) exposing lowermost redistribution layers among the plurality of redistribution layers; and
a plurality of bumps (810, para 43)
Shih does not show a plurality of bumps respectively disposed within the plurality of openings, each of the plurality of bumps respectively including an inner portion surrounded by the lower encapsulant and an outer portion protruding downwardly below the lower encapsulant, wherein the inner and outer portions each have a height perpendicular to the lower surface of the redistribution substrate, and the height of the inner portion is greater than the height of the outer portion.
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Link shows (Fig. 1) a plurality of bumps (116, para 21) respectively disposed within the plurality of openings (openings made for bumps), each of the plurality of bumps respectively including an inner portion (116 within 114) surrounded by the lower encapsulant (114, para 21) and an outer portion (116 below the 114 layer) protruding downwardly below the lower encapsulant, wherein the inner and outer portions each have a height perpendicular to the lower surface of the redistribution substrate, and the height of the inner portion (H1) is greater than the height of the outer portion (H2, as shown above).
2. Claim(s) 9, 11, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Link as applied to claim 1 or 15 above, further in view of US 20200212020 A1 (Zhang).
Regarding claim 9, Shih as previously modified with Link shows lower surface of the lower encapsulant and a lower surface of the passive component.
Shih as previously modified with Link does not show wherein a lower surface of the lower encapsulant and a lower surface of the passive component are coplanar.
Zhang shows (Fig. 5A-5E) wherein a lower surface of the lower encapsulant (533, para 47) and a lower surface of the passive component (190, capacitor, para 46) are coplanar.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Zhang, with coplanar passive device, to the invention of Shih.
The motivation to do so is that the selection of an art recognized passive device of Zhang is suitable for the intended use of Shih as previously modified with Link (MPEP §2144.07).
Regarding claim 11, Shih as previously modified with Link and Zhang shows wherein a height of the lower encapsulant (Zhang, 533) is in a range of about 10 µm to about 150 µm (para 20, since the height of capacitor is same as the height of lower encapsulant).
Regarding claim 16, Shih as previously modified with Link shows the plurality of bumps.
Shih as previously modified with Link is silent regarding wherein the plurality of bumps comprise tin (Sn) or an alloy of tin (Sn).
Zhang shows (Fig. 5A-5E) wherein the plurality of bumps (150, para 24) comprise tin (Sn) or an alloy of tin (Sn).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Zhang, with bump material, to the invention of Shih as previously modified with Link.
The motivation to do so is that the combination produces the predictable result of higher-temperature withstanding solder (para 24).
3. Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Link as applied to claim 12 above, further in view of US 20220328467 A1 (Chen).
Regarding claim 13, Shih as previously modified with Link shows the first semiconductor chip and the second semiconductor chip.
Shih as previously modified with Link does not show wherein the first semiconductor chip comprises a logic chip, and the second semiconductor chip comprises a memory chip.
Chen shows (Fig. 9) wherein the first semiconductor chip (50A or 50B, para 32) comprises a logic chip, and the second semiconductor chip (50C, para 32) comprises a memory chip.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Chen, with logic and memory chip, to the invention of Shih as previously modified with Link.
The motivation to do so is that the selection of an art recognized devices of Chen is suitable for the intended use of Shih as previously modified with Link (MPEP §2144.07).
Regarding claim 14, Shih as previously modified with Link shows the redistribution substrate, the first semiconductor chip and the second semiconductor chip.
Shih as previously modified with Link does not show further comprising: a base substrate disposed below the redistribution substrate, and including an interconnection circuit to which the plurality of bumps are connected; and
a heat sink disposed on the first semiconductor chip and the second semiconductor chip.
Chen shows (Fig. 9) further comprising: a base substrate (200, para 47) disposed below the redistribution substrate (104, para 38), and including an interconnection circuit to which the plurality of bumps (124, para 41) are connected; and
a heat sink disposed on the first semiconductor chip and the second semiconductor chip (48).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Chen, with base substrate and heat sink, to the invention of Shih as previously modified with Link.
The motivation to do so is that the combination produces the predictable result of cooling the chips and attaching the structure to another component such as motherboard or PCB (para 45).
4. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Link as applied to claim 15 above, further in view of US 20220230967 A1 (Park).
Regarding claim 18, Shih as previously modified with Link shows the upper encapsulant and the lower encapsulant.
Shih as previously modified with Link does not show wherein the upper encapsulant and the lower encapsulant comprise the same material.
Park shows (Fig. 2J) the upper encapsulant (130, para 26) and the lower encapsulant (140, para 30) comprise the same material (epoxy).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have upper and lower encapsulant according to the teaching of “Park”, since it has been held to be within the general skill of a worker in the art to select a known material of encapsulant on the basis of its suitability for the intended use as a matter of obvious design choice, In re Leshin, 125 USPQ 416 (CCPA 1960).
Moreover, the court has held that a simple substitution of one known element for another to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
5. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih, as applied to claim 19 above, further in view of US 20180151530 A1 (Chen2).
Regarding claim 20, Shih shows conductive members electrically connecting the passive components to the redistribution layers.
Shih does not show an underfill member surrounding the conductive members between the redistribution substrate and the passive components.
Chen2 shows (Fig. 9) an underfill member (148, para 37) surrounding the conductive members between the redistribution substrate (132, para 37) and the passive components (140,142, IPD or passive components, para 36).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Chen2, with underfill, to the invention of Shih.
The motivation to do so is that the combination produces the predictable result of improve reliability of the final structure while reducing manufacturing costs (para 12).
Allowable Subject Matter
Claims 4-6,17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein each of the plurality of bumps further comprises a third portion disposed between the first and second portions that is spaced apart from the inner wall”.
Regarding claim 17, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the inner portions of the plurality of bumps are spaced apart from inner walls of the plurality of openings in some regions”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812