DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is response to the application filed on 10/16/2023. Claim 1 is pending and herein considered.
Oath/Declaration
The receipt of oath/declaration is acknowledged.
Drawings
The drawings were received on 10/16/2023. These drawings are reviewed and accepted by the Examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 11/16/2023 (which documents listed have been submitted in the U.S Application No. 16/584,811 filed 10/16/2020 and 01/14/2021), and IDS submitted on 10/23/2025, are in compliance with the provisions of 37 CRR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim(s) 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-25 of U.S. Patent No. 11,791,938 (Application no. 16/584,811). Although the conflicting claims are not identical, they are not patentably distinct from each other because claims of the instant application merely broaden the scope of the claims of U.S. Patent No. 11,791,938 (Application no. 16/584,811) by eliminating the elements and their functions of the claims. It has been held that the omission an element and its function is an obvious expedient if the remaining elements perform the same function as before. In re Karlson, 136 USPQ 184 (CCPA). Also note Ex parte Rainu, 168 USPQ 375 (Bd.App.1969); omission of a reference element whose function is not needed would be obvious to one skilled in the art and where the patent and the application are directed to two or more decoders to decode, in parallel, a first compressed portion of one or more fifth generation new radio ("5G NR") signals using a first portion of a software graph indicating how the first compressed portion of the 5G NR signal is compressed and a second compressed portion of the 5G NR signal using a second portion of the software graph indicating how the second compressed portion of the 5G NR signal is compressed; and one or more circuits to cause the decoded first and second compressed portions of the 5G NR signal to be combined. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify claims 1-25 of U.S. Patent No. 11,791,938 (Application no. 16/584,811) to teach the invention of the claim 1 of the current application.
Instant Application 18/380,571
U.S. Patent No. 11,791,938
For claim 1:
1. A system comprising: two or more decoders to decode, in parallel, a first compressed portion of one or more fifth generation new radio (“5G NR”) signals using a first portion of a software graph indicating how the first compressed portion of the 5G NR signal is compressed and a second compressed portion of the 5G NR signal using a second portion of the software graph indicating how the second compressed portion of the 5G NR signal is compressed; and one or more circuits to cause the decoded first and second compressed portions of the 5G NR signal to be combined.
For claim 1:
1. A processor comprising: two or more decoders to decode, in parallel, a first compressed portion of one or more fifth generation new radio ("5G NR") signals using a first portion of a software graph indicating how the first compressed portion of the 5G NR signal is compressed and a second compressed portion of the 5G NR signal using a second portion of the software graph indicating how the second compressed portion of the 5G NR signal is compressed; and one or more circuits to cause the decoded first and second compressed portions of the 5G NR signal to be combined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lam et al. (2020/0252080) in view of IEEE, Dimarkis et al. :“LDPC codes compressed sensing”, IEEE Transactions on information theory Vol.58, No.5, May 2012 (pages 3093-3114).
For claim 1:
Lam discloses a processor comprising: two or more decoders to decode, in parallel (see Lam, at least Figure 2, paragraphs [0008]-[0009]; [0028]-[0032]; a parallel LDPC decoder implements a configuration having a plurality of code blocks, wherein each active region processes a respectively code block which the decoder logic active portions of parallel LDPC decoder, (note: at {0009]; [0039]; describes Parallel LDPC decoders of embodiments may additionally or alternatively provide enhanced operational aspects (e.g., 5G base stations may be enabled to support a large number of users in standby mode through use of parallel LDPC decoders of embodiments and is not a limitation with respect to application of the concepts of the present invention. in an implementation for a 5G network,). Parallel LDPC decoders of embodiments, providing both efficiencies with respect to processing and power consumption, are well suited for use with respect to high performance, broadband data networks, such as those of the evolving 5G cellular standard)), a first compressed portion of one or more fifth generation new radio ("5G NR") signals using a first portion of a software graph indicating how the first compressed portion of the 5G NR signal is compressed and a second compressed portion of the 5G NR signal using a second portion of the software graph indicating how the second compressed portion of the 5G NR signal is compressed; and one or more circuits to cause the decoded first and second compressed portions of the 5G NR signal to be combined (see Lam, at least Figure 2, 3A and paragraphs [0029]-[0033]; Figure 3A shows both a base graph matrix (BG) and a Tanner graph construction and the overall input of the parallel LDPC decoder may be formed by combining code blocks that are using the same BO matrix index (e.g., the table above and parallel LDPC decoder 200 is capable of decoding code blocks of multiple encoded data streams ( e.g., received signals from a plurality of connected terminals) in parallel for efficient and flexible processing).
Dimakis, from the same or similar fields of endeavor, discloses what Lam fails: compressed sensing linear programming decoding (CS-LPD), where CC-LPD of the binary linear channel code that is obtained by viewing this measurement matrix as a binary parity-check matrix (see Dimakis, at least abstract, section VII; graph-cover decoder of some Tanner graph (see figure 2) and compressed sensing setup will be over the complex numbers. Also see section IX; established a mathematical connection between channel coding and compressed sensing LP relaxations),
Therefore, it would have been obvious statement before the effective filing date of the claimed invention to have a system comprises a method as taught by Dimakis. The motivation for doing this is to provide a system networks can define an analogous compressed sensing problem by assuming that the support of the sparse signal e is known to the decode.
Conclusion
The prior arts made or record and not relied upon are considered pertinent to applicant's disclosures. Paumier et al. (U.S 2007/0094565), discloses the source encoder compresses the data (for example using a standard such as MPEG, H264, etc.) so as to reduce the bit rate of the data to be transmitted. The channel encoder adds redundancy (for example by using an LDPC code) to enable the receiver 30 to correct potential errors due to the noise introduced into the transmission channel.
Pawlowski et al. (U.S 10,929,132), discloses a system to access a list data structure, a compressed list in a graph application (e.g., a compressed graphic list).
Kalache et al. (U.S 10,735,138), discloses a method for generating a code, a method for encoding and decoding data, and an encoder and a decoder performing the encoding and decoding are disclosed.
Pisek (U.S 9,100,052) discloses a low-density parity check (LDPC) encoding method and further includes obtaining a quasi-cyclic LDPC (QC-LDPC) convolutional code H-Matrix.
Andreev et al. (U.S 8,151,160), discloses the control circuit is used to configure sizes of the direct and reverse multi-size barrel shifters and numbers of the parity check units and the bit node units to cooperate with each other based on a block size of a particular low-density parity check (LDPC) code.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAN-HUONG TRUONG whose telephone number is (571) 270-5829. The examiner can normally be reached on Monday-Friday 8am-5pm.
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/LAN-HUONG TRUONG/Primary Examiner, Art Unit 2464
10/31/2025