DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to an Application filed on 10/17/2023.
Currently, claims 1-20 are examined as below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 10/17/2023. The IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Device Including a Field Effect Transistor
(Clean Version) Semiconductor Device Including a Field Effect Transistor
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 is indefinite, because the limitation “a first conductivity type” renders the claim indefinite. It is unclear whether such first conductivity type is the same first conductivity type as recited in the base claim 11.
Note the dependent claim 17 necessarily inherit the indefiniteness of the claims on which they depend.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1-15 and 18-20 are allowed.
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Regarding independent claim 1, US 2018/0151576 A1 to Lee in Figs. 8, 9C and Annotated Fig. 9C teaches a semiconductor device (Fig. 8 & ¶ 51, semiconductor device), comprising:
a first substrate 100 (Fig. 9C & ¶ 52, substrate 100) that includes a first region R1 (Annotated Fig. 9C) and a second region R2 (Annotated Fig. 9C);
an active pattern FN (Fig. 9C & ¶ 56, active pattern FN) disposed on the first region R1 (Annotated Fig. 9C);
a source/drain pattern SD (Fig. 9C & ¶ 33, source/drain region SD) disposed on the active pattern FN;
a through contact VI (Fig. 9C & ¶ 36, via VI) disposed on the second region R2 (Annotated Fig. 9C);
a first metal layer 121 (Fig. 9C & ¶ 73, second conductive pattern 121 includes a metal) disposed on the through contact VI;
a second substrate 100 (Fig. 9C & ¶ 52, substrate 100) disposed on (i.e., in proximity to) the first metal layer 121, wherein the second substrate 100 includes an impurity region SD (Fig. 9C & ¶ 61, source/drain region SD is an impurity region).
However, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 1, a lower bonding pad disposed between the first metal layer and the second substrate; an upper bonding pad disposed on the lower bonding pad; and a power delivery network layer disposed on a bottom surface of the first substrate, wherein the lower bonding pad and the upper bonding pad are in contact with each other, wherein the through contact is connected to the lower bonding pad, and wherein the impurity region is connected to the upper bonding pad.
Therefore, independent claim 1 is allowed.
Claims 2-10 are allowed, because they depend from the allowed claim 1.
Regarding independent claim 11, Lee in Figs. 8, 9C and Annotated Fig. 9C teaches a semiconductor device (Fig. 8 & ¶ 51, semiconductor device), comprising:
a first substrate 100 (Fig. 9C & ¶ 52, substrate 100) that includes a first region R1 (Annotated Fig. 9C) and a second region R2 (Annotated Fig. 9C);
an active pattern FN (Fig. 9C & ¶ 56, active pattern FN) disposed on the first region R1 (Annotated Fig. 9C);
a source/drain pattern SD (Fig. 9C & ¶ 33, source/drain region SD) disposed on the active pattern FN;
a first through contact VI1 (Annotated Fig. 9C & ¶ 36, via VI1) and a second through contact VI2 (Annotated Fig. 9C & ¶ 36, via VI2) disposed on the second region R2, wherein the first through contact VI1 and the second through contact VI2 are spaced apart from each other (Annotated Fig. 9C);
a first metal layer 121 (Fig. 9C & ¶ 73, second conductive pattern 121 includes a metal) disposed on the first and second through contacts VI1, VI2;
a second substrate 100 (Fig. 9C & ¶ 52, substrate 100) disposed on (i.e., in proximity to) the first metal layer 121, wherein the second substrate includes a first impurity region SD1 (Annotated Fig. 9C & ¶ 61, source/drain region SD1 is an impurity region) and a second impurity region SD1 (Annotated Fig. 9C & ¶ 61, source/drain region SD1 is an impurity region), wherein the first impurity region SD1 includes impurities having a first conductivity type (¶ 61, n-type impurity or p-type impurity), and the second impurity region SD2 (Annotated Fig. 9C & ¶ 61, source/drain region SD2 is an impurity region) includes impurities having a second conductivity type (¶ 61, p-type impurity or n-type impurity), and
wherein the impurities having the first conductivity type are different from the impurities having the second conductivity type (¶ 61).
However, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 11, a plurality of lower bonding pads disposed between the first metal layer and the second substrate; a plurality of upper bonding pads disposed on the lower bonding pads; and a power delivery network layer disposed on a bottom surface of the first substrate, wherein the first and second through contacts are electrically connected to the first and second impurity regions, respectively.
Therefore, independent claim 11 is allowed.
Claims 12-15 and 18 are allowed, because they depend from the allowed claim 11.
Regarding independent claim 19, Lee in Figs. 1-2, 4, 8, 9A-9C and Annotated Fig. 9C teaches a semiconductor device (Fig. 8 & ¶ 51, semiconductor device), comprising:
a first power line PL1 (Figs. 8, 9A-9B & ¶ 19, first power line PL1) and a second power line PL2 (Fig. 8 & ¶ 19, second power line PL2) disposed on a first substrate 100 (Figs. 4, 8, 9A-9C & ¶ 33, substrate 100 including an active pattern FN) and spaced apart from each other in a first direction D2 (Fig. 8 & ¶ 34, second direction D2), wherein the first and second power lines PL1, PL2 extend parallel to each other in a second direction D1 (Fig. 8 & ¶ 36, first direction D1);
a logic cell C1, C2 (Figs. 1-2, 8 & ¶ 19, memory cell C1, C2) disposed between the first and second power lines PL1, PL2 and spaced apart from each other in the second direction D1;
a first active pattern FN (Figs. 8, 9C & ¶ 56, active pattern FN) and a second active pattern FN (Figs. 8, 9C & ¶ 56, active pattern FN);
a first channel pattern AF1 (Annotated Fig. 9C & ¶ 33, channel region AF1) and a first source/drain pattern SD1 (Annotated Fig. 9C & ¶ 33, source/drain region SD1) disposed on the first active patter FN;
a second channel pattern AF2 (Annotated Fig. 9C & ¶ 33, channel region AF2) and a second source/drain pattern SD2 (Annotated Fig. 9C & ¶ 33, source/drain region SD2) disposed on the second active pattern FN, wherein the second source/drain pattern SD2 has a conductivity type different from a conductivity type of the first source/drain pattern SD1 (¶ 61);
a gate electrode GE1, GE2 (Fig. 9C & ¶ 59, first gate electrode GE1, second gate electrode GE2) disposed on the first and second channel patterns AF1, AF2 (Annotated Fig. 9C);
a gate dielectric layer GI (Annotated Fig. 9C & ¶ 59, gate dielectric pattern GI) disposed between the gate electrode GE1, GE2 and the first and second channel patterns AF1, AF2;
a gate spacer GS (Fig. 9C & ¶ 59, gate spacer GS) disposed on a sidewall of the gate electrode GE1, GE2;
a gate capping pattern CP (Fig. 9C & ¶ 59, capping pattern CP) disposed on the gate electrode GE1, GE2;
an interlayer dielectric layer 110 (Annotated Fig. 9C & ¶ 59, first interlayer dielectric layer 110) that covers the first and second source/drain patterns SD1, SD2 and the gate capping pattern CP;
an active contact AC1, AC2 (Annotated Fig. 9C & ¶ 65, first active contact AC1, second active contact AC2) that penetrates the interlayer dielectric layer 110 and are electrically connected to a corresponding one of the first and second source/drain patterns SD1, SD2;
a first through contact VI (Fig. 8 & ¶ 36, via VI) and a second through contact VI (Fig. 9 & ¶ 36, via VI) respectively connected to the first and second power lines PL1, PL2 (Fig. 8);
a second substrate 120 (Fig. 9C & ¶ 59, second interlayer dielectric layer 120) disposed on (i.e., in proximity to) the first and second through contacts VI.
However, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 19, a logic cell and a passive element cell disposed between the first and second power lines and spaced apart from each other in the second direction; a first active pattern and a second active pattern disposed on the logic cell and spaced apart from each other in the first direction; a gate contact that penetrates the interlayer dielectric layer and the gate capping pattern and is electrically connected to the gate electrode; a first through contact and a second through contact disposed on the passive element cell and respectively connected to the first and second power lines; a second substrate disposed on the first and second through contacts, wherein the second substrate includes a first impurity region and a second impurity region that have different conductivity types from each other; a plurality of lower bonding pads disposed between the second substrate and the first and second through contacts and a plurality of upper bonding pads disposed on the lower bonding pads; and a power delivery network layer disposed on the first substrate, wherein the lower bonding pads are correspondingly in contact with the upper bonding pads, and wherein the first and second through contacts are electrically connected to the first and second impurity regions, respectively, through the lower and upper bonding pads.
Therefore, independent claim 19 is allowed.
Claim 20 is allowed, because claim 20 depends from the allowed claim 19.
Claims 16-17 are rejected.
Claims 16-17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 16 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 16, a third through contact disposed on the second region and spaced apart from the first and second through contacts; and a third impurity region is spaced apart from the first impurity region with the second impurity region disposed therebetween, wherein the third impurity region includes impurities having a first conductivity type.
Claim 17 would be allowable, because claim 17 depends from the allowable claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0012147 A1 to Chu et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817