Attorney’s Docket Number: SAM-61316
Filing Date: 10/17/2023
Claimed Foreign Priority Date: 02/15/2023 (KR10-2023-0019717)
Applicants: Kim et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the application and preliminary amendment filed on 10/17/2023.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/380,848 and the preliminary amendment filed on 10/17/2023 have been entered. Applicant cancelled claim 21. Accordingly, pending in this Office Action are claims 1-20.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the arrangement where “a first channel contacting an upper surface of the bit line and a sidewall of the gate insulation pattern” AND “a second channel on the first channel” in claims 1-2 must be shown or the features canceled from the claims. Instead, the Drawings (see, e.g., Fig. 26) depict a first channel 215 contacting an upper surface of the bit line 130 and a second channel 705 on the first channel, wherein the first channel 215 does not contact a sidewall of the gate insulation pattern 225, due to intervening second channel 705.
Claim 11 recites the limitations “a first channel contacting an upper surface of the bit line and a sidewall of the gate insulation pattern” AND “a second channel on the first channel”, thus raises issues similar to the ones discussed above.
Claim 17 recites the limitations “a channel contacting an upper surface of each of the bit lines and a sidewall in the first direction of the gate insulation pattern, the channel including an amorphous oxide semiconductor material; a first channel contacting an upper portion of a sidewall of the channel in the first direction, the first channel including spinel IGZO”. Instead, the Drawings (see, e.g., Fig. 26 and Par. [0070]-[0071],[109]) depict a channel 215 contacting an upper surface of each of the bit lines 130, the channel 215 including spinel IGZO; a first channel 705 contacting an upper portion of a sidewall of the channel 215 in the first direction, the first channel including an amorphous oxide semiconductor material, wherein the channel 215 does not contact a sidewall of the gate insulation pattern 225, due to intervening first channel 705.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. No new matter should be entered. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
- Claims 1-2 and 11 recite in part “a first channel contacting an upper surface of the bit line and a sidewall of the gate insulation pattern” AND “a second channel on the first channel”. The disclosure as originally filed (see, e.g., Fig. 26 and Par. [0106]-[0110]) is silent about the claimed arrangement.
- Claim 17 recites the limitations “a channel contacting an upper surface of each of the bit lines and a sidewall in the first direction of the gate insulation pattern, the channel including an amorphous oxide semiconductor material; a first channel contacting an upper portion of a sidewall of the channel in the first direction, the first channel including spinel IGZO”. The disclosure as originally filed (see, e.g., Fig. 26 and Par. [0106]-[0110]) is silent about the claimed arrangement, as well as the claimed compositions of the channel and first channel.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 2-6 and 11-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 2 recites the limitation “a second channel on the first channel, the second channel including a material having a lattice matching with IGZO.”. However, claim 1, from which claim 2 depends already requires “a first channel contacting an upper surface of the bit line and a sidewall of the gate insulation pattern”, and the original written description is devoid of an arrangement having “a first channel contacting an upper surface of the bit line and a sidewall of the gate insulation pattern” AND “a second channel on the first channel”.
Claims 3-6 depend from claim 2 thus inherit the deficiencies identified supra.
Claim 11 recites the limitation “a first channel contacting an upper surface of the bit line and a sidewall of the gate insulation pattern” AND “a second channel on the first channel”, thus raises issues similar to the ones discussed above.
Claims 12-16 depend from claim 11 thus inherit the deficiencies identified supra.
Claim 17 recites the limitations “a channel contacting an upper surface of each of the bit lines and a sidewall in the first direction of the gate insulation pattern, the channel including an amorphous oxide semiconductor material; a first channel contacting an upper portion of a sidewall of the channel in the first direction, the first channel including spinel IGZO”, and the original written description is devoid of an arrangement having “a channel contacting an upper surface of each of the bit lines and a sidewall in the first direction of the gate insulation pattern” AND “a first channel contacting an upper portion of a sidewall of the channel in the first direction”, as well as “the channel including an amorphous oxide semiconductor material” and “the first channel including spinel IGZO”.
Claims 18-20 depend from claim 17 thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1, 7, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et. al (US2022/0384661).
Regarding Claim 1, Cho (see, e.g., Figs. 1-3) shows all aspects of the instant invention, including a semiconductor device (e.g., semiconductor device 100) comprising:
- a bit line (e.g., bitline BL/110) on a substrate (e.g., substrate 101)
- a gate electrode (e.g., one of gate electrode 150a,150b) on the bit line
- a gate insulation pattern (e.g., gate insulating layer 140) on a sidewall of the gate electrode
- a first channel (e.g., channel layer 130) contacting an upper surface of the bit line and a sidewall of the gate insulation pattern, the first channel including spinel IGZO (see, e.g., Par. [0035])
- a contact plug (e.g., interconnection portion 190) contacting an upper surface of the first channel
Regarding Claim 7, Cho (see, e.g., Fig. 2A) shows that a cross-section in a direction of the first channel (e.g., direction D1) has a shape of a cup.
Regarding Claim 9, Cho (see, e.g., Fig. 2A) shows that the contact plug (e.g., 190) has a lower portion and an upper portion, the lower portion contacting the upper surface of the first channel and having a first width, and the upper portion being disposed on the lower portion and having a second width that is greater than the first width.
Regarding Claim 10, Cho (see, e.g., Fig. 2A) shows a capacitor (e.g., data storage element/capacitor DS) on the contact plug.
Claim 1-5, 7-8, 10-13, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et. al (US2023/0035916).
Regarding Claim 1, Kim (see, e.g., Figs. 6-7, 12-13, or 18-19) shows all aspects of the instant invention, including a semiconductor device comprising:
- a bit line (e.g., bitline BL/220) on a substrate (e.g., substrate 200)
- a gate electrode (e.g., one of gate electrode 250a,250b) on the bit line
- a gate insulation pattern (e.g., gate dielectric layer 240) on a sidewall of the gate electrode
- a first channel (e.g., oxide semiconductor layer 14) contacting an upper surface of the bit line (e.g., 14 at least in electrical contact with upper surface of 220) and a sidewall of the gate insulation pattern, the first channel including spinel IGZO (see, e.g., Par. [0041]: spinel IGZO)
- a contact plug (e.g., upper contact layer 270) contacting an upper surface of the first channel
Regarding Claim 2, Kim (see, e.g., Figs. 6-7) shows a second channel (e.g., oxide semiconductor layer 12) on the first channel, the second channel including a material having a lattice matching with IGZO (see, e.g., Par. [0038]: GZO).
Regarding Claim 3, Kim (see, e.g., Par. [0038]) shows that the second channel (e.g., 12) includes at least one of GaZn2O4(GZO), ZnIn2O4, Zn2SnO4, Zn2TiO4, Ga2O3, TiN, SiC, RuO2 and ZnAl204.
Regarding Claim 4, Kim (see, e.g., Par. [0038]) shows that the second channel (e.g., 12) includes GaZn2O4(GZO).
Regarding Claim 5, Kim (see, e.g., Figs. 6-7) shows that an upper surface of the second channel contacts the contact plug (e.g., upper surface of 12 at least in electrical contact with 270).
Regarding Claim 7, Kim (see, e.g., Figs. 6-7, 12-13, or 18-19) shows that a cross-section in a direction of the first channel (e.g., direction Y2) has a shape of a cup.
Regarding Claim 8, Kim (see, e.g., Figs. 6-7, 12-13, or 18-19) shows that the first channel (e.g., 14) has a top surface lower than an upper surface of the gate insulation pattern (e.g., 240).
Regarding Claim 10, Kim (see, e.g., Figs. 6-7, 12-13, or 18-19) shows a capacitor (e.g., capacitor structure 290) on the contact plug.
Regarding Claim 11, Kim (see, e.g., Figs. 6-7) shows all aspects of the instant invention, including a semiconductor device comprising:
- a bit line (e.g., bitline BL/220) on a substrate (e.g., substrate 200)
- a gate electrode (e.g., one of gate electrode 250a,250b) on the bit line
- a gate insulation pattern (e.g., gate dielectric layer 240) on a sidewall of the gate electrode
- a channel structure including:
a first channel (e.g., oxide semiconductor layer 14) contacting an upper surface of the bit line (e.g., 14 at least in electrical contact with upper surface of 220) and a sidewall of the gate insulation pattern, the first channel including spinel IGZO (see, e.g., Par. [0041]: spinel IGZO)
a second channel (e.g., oxide semiconductor layer 12) on the first channel, the second channel including a material having a lattice matching with IGZO (see, e.g., Par. [0038]: GZO)
a contact plug (e.g., upper contact layer 270) contacting an upper surface of the channel structure
Regarding Claim 12, Kim (see, e.g., Par. [0038]) shows that the second channel (e.g., 12) includes at least one of GaZn2O4(GZO), ZnIn2O4, Zn2SnO4, Zn2TiO4, Ga2O3, TiN, SiC, RuO2 and ZnAl204.
Regarding Claim 13, Kim (see, e.g., Par. [0038]) shows that the second channel (e.g., 12) includes GaZn2O4(GZO).
Regarding Claim 16, Kim (see, e.g., Figs. 6-7) shows that the channel structure has a top surface lower than an upper surface of the gate insulation pattern (e.g., 240).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose 1T-1C DRAM devices having a channel layer comprising spinel or crystalline IGZO, and comprising features similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814