Attorney’s Docket Number: SAM-61312
Filing Date: 10/17/2023
Claimed Foreign Priority Date: 03/20/2023 (KR10-2023-0035750)
Applicants: Kang et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the application filed on 10/17/2023.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/380,854 filed on 10/17/2023 has been entered. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et. al (US2015/0130046).
Regarding Claim 1, Lin (see, e.g., Figs. 63-64 and Annotated Fig. 64) shows all aspects of the instant invention, including a semiconductor package (e.g., package-on-package assembly 400) comprising:
- a substrate (e.g., interposer 11’/ first buildup circuitry 301)
- a semiconductor die (e.g., chip 13) on the substrate
- a heat spreader (e.g., metallic heat spreader 22) covering the semiconductor die and including an upper plate portion (e.g., portion of 22 above 13), a base portion (e.g., portions of 22 surrounding through holes 401), and a sidewall portion connecting the upper plate portion to the base portion (e.g., portions of 22 exposed to cavity 215), wherein the upper plate portion and the sidewall portion define an underlying cavity (see, Annotated Fig. 64)
- wherein the base portion is disposed on the substrate, extends from an exterior side of the sidewall portion in a horizontal direction, includes a plurality of first through holes (e.g., through holes 401), has a bottom surface at the same level as a bottom surface of the sidewall portion, and has a height in a vertical direction from a lowermost portion to an uppermost portion thereof less than or equal to that of the sidewall portion (see, e.g., Fig. 64).
Regarding Claim 2, Lin (see, e.g., Fig. 64 and Par. [0083]) shows that the heat spreader further includes an insulating layer (e.g., balancing layer 311 of epoxy resin, glass-epoxy, or polyimide) conformally disposed on an inner surface of each first through hole of the plurality of first through holes.
Regarding Claim 7, Lin (see, e.g., Fig. 64 and Par. [0078]) shows that the heat spreader includes an electrically conductive material (e.g., copper, aluminum, stainless steel or their alloys).
Regarding Claim 8, Lin (see, e.g., Fig. 64 and Par. [0090]) discloses that connecting layer 403 formed inside through holes 401 can be a hollow tube that covers the inner sidewall of 401 or a metal post filling 401, which would have a horizontal cross-section substantially shaped as a circle. Therefore, Lin implicitly shows that each first through hole (e.g., 401) among the plurality of first through holes has a cross- section shape of a circle, an ellipse, or a polygon in the horizontal direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et. al (US2015/0130046).
Regarding Claim 9, Lin (see, e.g., Fig. 64 and Par. [0090],[0139]) discloses that through holes 401 widths must be sufficient to form connecting layer 403 therein as a hollow tube covering the inner sidewall of the through holes or as a metal post filling said through holes, so as to enable electrical connectivity between bottom buildup circuitry 301 and top buildup circuitry 302, and achieve the package-on-package assembly 400. Therefore, Lin recognizes the width of through holes 401 as a result effective variable.
Accordingly, the specific first through hole width claimed by the applicant, i.e., a width of 55 um to 315 um, is only considered to be the “optimum” through hole width disclosed by Lin that a person having ordinary skill in the art would have been able to obtain using routine experimentation based, among other things, on current drive of the POP assembly, through hole via resistance vs. heat sink thickness, etc. (see In re Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as through holes are formed with a width sufficient to enable proper connectivity between various buildup circuitries or chips in the POP arrangement, as already suggested by Lin. Accordingly, Lin teaches that each first through hole among the plurality of first through holes has a width of 55 um to 315 um.
Allowable Subject Matter
Claims 10-20 are allowable.
Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 10, the prior art of record fails to disclose or suggest a semiconductor package comprising: wherein the supporting part is disposed on the first redistribution layer structure, extends from an exterior side of the sidewall part in a horizontal direction, includes a plurality of first through holes, has a bottom surface at the same level as the bottom surface of the sidewall part, and has a height of less than or equal to that of the sidewall part; a molding material molding the first semiconductor die, the heat spreader, and the plurality of conductive posts, and disposed on the first redistribution layer structure; and a second semiconductor die on the second redistribution layer structure.
Regarding Claim 15, the prior art of record fails to disclose or suggest a semiconductor package comprising: a three-dimensional integrated circuit (3D IC) structure including a first semiconductor die on the front side redistribution layer structure and a second semiconductor die on the first semiconductor die; wherein the upper plate portion is disposed on the first semiconductor die and includes a through opening in which the second semiconductor die is disposed; a molding material molding the three-dimensional integrated circuit structure, the heat slug, and the plurality of conductive posts; and a third semiconductor die on the back side redistribution layer structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose semiconductor packages comprising a heat spreader defining a cavity over a die, and having some aspects similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814