DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 2 is objected to because of the following informalities: please change “foremd” to “formed” and “isolatin” to “isolating” or “isolation”.
Claim 8 is objected to because of the following informalities: please change “ftontside” to “frontside” and change “conneced” to “connect”.
Claim 11 is objected to because of the following informalities: in the last 2 lines, please change “migligned to “misaligned”.
Claim 18 is objected to because of the following informalities: please change “ftontside” to “frontside” and change “conneced” to “connect”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation “the backside gate contact structure contacts the 1st contact spacer”. There is insufficient antecedent basis for “the 1st contact spacer” in the claim. Claim 16 should be dependent from claim 15.
Claims 17-18 are rejected since they inherit the deficiency from claim 16 which they are dependent from.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
For the purpose of compact prosecution, multiple rejections are made with different references based on different interpretations. A single amendment could be made to overcome all possible rejections with available references.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang (U.S. Patent Application Publication No. 2024/0355708).
Regarding to claim 1, Huang teaches a semiconductor device comprising:
a 1st source/drain region (Fig. 47C, element 800a/left, [0065], last 3 lines);
a 2nd source/drain region (Fig. 47C-D, element 800a/right, [0065], last 3 lines);
a channel structure connecting the 1st source/drain region to the 2nd source/drain region (Fig. 47C, element 205, [0065], lines 14-15);
a gate structure configured to control the channel structure (Fig. 47C, element 308, [0065], line 6);
a backside isolation structure at a lower portion of the semiconductor device (Fig. 47C, Fig. 47D, element 206, [0065], last 2 lines);
a backside source/drain contact structure connected to a bottom surface of the 1st source/drain region in the backside isolation structure (Figs. 47C-D, element 292, [0066], lines 2-3);
a 1st contact spacer on the backside source/drain contact structure (Figs. 47C-D, element 393, [0069], line 9, please also see Fig. 47A for the label),
wherein the 1st contact spacer is configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure ([0052], lines 4-8, since the spacer layer 393 is a dielectric layer that encapsulates the backside source/drain contact structure 292, it isolates the backside source/drain contact structure from another circuit element in the backside isolation structure).
PNG
media_image1.png
808
1105
media_image1.png
Greyscale
Regarding to claim 2, Huang teaches the 1st contact spacer is formed on a side surface of the backside source/drain contact structure (Fig. 47C, Fig. 49), and comprises an isolation material ([0052], lines 4-8).
Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung et al. (U.S. Patent No. 11,699,742).
Regarding to claim 1, Chung teaches a semiconductor device comprising:
a 1st source/drain region (Fig. 15D, element 260c, column 5, lines 61-64);
a 2nd source/drain region (Fig. 15D, element 260d, column 5, lines 61-64);
a channel structure connecting the 1st source/drain region to the 2nd source/drain region (Fig. 15D, element 215, column 5, lines 53-54);
a gate structure configured to control the channel structure (Fig. 15D, element 240, column 5, line 56);
a backside isolation structure at a lower portion of the semiconductor device (Fig. 15D-E, element 230, column 12, lines 10-11);
a backside source/drain contact structure connected to a bottom surface of the 1st source/drain region in the backside isolation structure (Fig. 15D, element 282, column 14, lines 4-5);
a 1st contact spacer on the backside source/drain contact structure (Fig. 15D, element 304, column 135, line 6),
wherein the 1st contact spacer is configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure (since the spacer layer 304 is a dielectric layer that encapsulates the backside source/drain contact structure 282, it isolates the backside source/drain contact structure from another circuit element in the backside isolation structure).
Regarding to claim 2, Chung teaches the 1st contact spacer is formed on a side surface of the backside source/drain contact structure (Fig. 15D), and comprises an isolation material (column 13, lines 5-6).
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kang (U.S. Patent Application Publication No. 2024/0186219).
Regarding to claim 1, Kang teaches a semiconductor device comprising:
a 1st source/drain region (Figs. 20D-E, element 132B, [0125], line 5);
a 2nd source/drain region (Figs. 20D-E, element 132A, [0125], line 5);
a channel structure connecting the 1st source/drain region to the 2nd source/drain region (Figs. 20D-E, element 108, [0122], lines 3-4);
a gate structure configured to control the channel structure (Figs. 20D-E, element 142A, [0132], line 6;
a backside isolation structure at a lower portion of the semiconductor device (Figs. 20D-E, element 118, [0118], line 6);
a backside source/drain contact structure connected to a bottom surface of the 1st source/drain region in the backside isolation structure (Figs. 20D-E, element 160, [0147], lines 2-3);
a 1st contact spacer on the backside source/drain contact structure (Figs. 20D-E, element 114, [0147], lines 2-3);
wherein the 1st contact spacer is configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure (Figs. 20D-E, the backside source/drain contact structure 160 is isolated from the backside isolation structure 118 by the contact spacer 114, thus the backside source/drain contact structure is isolated from another circuit element in the backside isolation structure).
Regarding to claim 2, Kang teaches the 1st contact spacer is formed on a side surface of the backside source/drain contact structure (Fig. 20E), and comprises an isolation material ([0116], line 3, dielectric is isolation material).
Regarding to claim 3, Kang teaches a backside gate contact structure connected to a bottom surface of the gate structure (Fig. 20D, element 172, [0146], line 5).
Regarding to claim 4, Kang teaches the backside isolation structure is formed between the backside gate contact structure and the 1st contact spacer (Fig. 20E, the backside isolation structure 118 is formed between the backside gate contact structure 172 and the 1st contact spacer 114).
Regarding to claim 5, Kang teaches the backside gate contact structure contacts the 1st contact spacer (Fig. 20D, the backside gate contact structure 172 contacts the 1st contact spacer 114).
Regarding to claim 6, Kang teaches a placeholder structure connected to a bottom surface of the 2nd source/drain region (Fig. 11D, element 156); and a 2nd contact spacer on the placeholder structure (Fig. 11D, element 114), the 2nd contact spacer isolating the placeholder structure from another circuit element in the backside isolation structure (Fig. 11D, the 2nd contact spacer isolating the placeholder structure from the backside isolation structure, thus the 2nd contact spacer isolating the placeholder structure from another circuit element in the backside isolation structure).
Regarding to claim 7, Kang teaches the 2nd contact spacer comprises: a side spacer on a side surface of the placeholder structure (Fig. 11D, element 114); and a bottom spacer on a bottom surface of the placeholder structure (Fig. 11D, element 102).
Regarding to claim 8, Kang teaches a frontside source/drain contact structure connected to the 2nd source/drain region (Fig. 20E).
Regarding to claim 9, Kang teaches a backside gate contact structure connected to a bottom surface of the gate structure (Figs. 20D-E, element 172).
Regarding to claim 10, Kang teaches the backside gate contact structure is formed between the 1st contact spacer and the 2nd contact spacer (Fig. 20E).
Regarding to claim 11, Kang teaches a semiconductor device comprising:
a 1st source/drain region (Figs. 20D-E, element 132B, [0125], line 5);
a 2nd source/drain region (Figs. 20D-E, element 132A, [0125], line 5);
a channel structure connecting the 1st source/drain region to the 2nd source/drain region (Figs. 20D-E, element 108, [0122], lines 3-4);
a gate structure configured to control the channel structure (Figs. 20D-E, element 142A, [0132], line 6;
a backside isolation structure at a lower portion of the semiconductor device (Figs. 20D-E, element 118, [0120], lines 1-3);
a backside gate contact structure connected to a bottom surface of the gate structure in the backside isolation structure (Figs. 20D-E, element 172, [0146], line 5),
wherein the backside gate contact structure is misaligned with the bottom surface of the gate structure to be closer to the 2nd source/drain region than the 1st source/drain region (Fig. 20E).
Regarding to claim 12, Kang teaches a portion of the backside gate contact structure does not contact the bottom surface of the gate structure (Figs. 20D-E, the portion of the backside gate contact structure 172 under the spacer 114 does not contact the bottom surface of the gate structure).
Regarding to claim 13, Kang teaches the portion of the backside gate contact structure that does not contact the bottom surface of the gate structure contacts a bottom surface of an inner spacer formed between the gate structure and the 1st source/drain region (Fig. 20D, the portion of the backside gate contact structure 172 that does not contact the bottom surface of the gate structure contacts bottom surface of an inner spacer 114 formed between the gate structure 142 and the 1st source/drain region 132A).
PNG
media_image2.png
737
1202
media_image2.png
Greyscale
Regarding to claim 14, Kang teaches the backside gate contact structure is formed to be closer to the 1st source/drain region than the 2nd source/drain region (Fig. 20E).
Regarding to claim 15, Kang teaches a backside source/drain contact structure connected to a bottom surface of the 1st source/drain region (Fig. 20E, element 160, [0147], lines 2-3); and a 1st contact spacer on the backside source/drain contact structure (Figs. 20D-E, element 114, [0147], lines 2-3), the 1st contact spacer configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure (Figs. 20D-E, the backside source/drain contact structure 160 is isolated from the backside isolation structure 118 by the contact spacer 114, thus the backside source/drain contact structure is isolated from another circuit element in the backside isolation structure).
Regarding to claim 16, Kang teaches the backside gate contact structure contacts the 1st contact spacer (Fig. 20E).
Regarding to claim 17, Kang teaches a placeholder structure connected to a bottom surface of the 2nd source/drain region (Fig. 11D, element 130, [0124], line 3); and a 2nd contact spacer on the placeholder structure (Fig. 11D, element 114), the 2nd contact spacer isolating the placeholder structure from another circuit element in the backside isolation structure (Fig. 11D, the 2nd contact spacer isolating the placeholder structure from the backside isolation structure, thus the 2nd contact spacer isolating the placeholder structure from another circuit element in the backside isolation structure).
Regarding to claim 18, Kang teaches a frontside source/drain contact structure connected to the 2nd source/drain region (Fig. 20E).
PNG
media_image3.png
711
1246
media_image3.png
Greyscale
Regarding to claim 19, Kang teaches a method of manufacturing a semiconductor device, comprising (the method steps are not claimed to impart in a specific order):
forming a placeholder structure on a bottom surface of a source/drain region (Fig. 8A-D, element 130, [0124], lines 3);
forming a contact spacer on the placeholder structure (Fig. 9D, element 114);
forming a backside gate contact structure on a bottom surface of a gate structure (Figs. 11C, the portion of gate contact 142 between spacers 114); and
replacing the placeholder structure with a backside source/drain contact structure such that the backside source/drain contact structure is surrounded by the contact spacer (Fig. 15D to Fig. 16D, replacing the placeholder structure 130 with backside source/drain contact structure 160 such that the backside source/drain contact structure 160 is surrounded by the contact spacer 114).
Regarding to claim 20, Kang teaches the backside gate contact structure is formed to contact the contact spacer (Fig. 11C, the backside gate contact structure contacts the contact spacer 114).
PNG
media_image4.png
691
1410
media_image4.png
Greyscale
Pertinent Art
For the benefits of the Applicant, US-11699742-B2, US-12362004-B2, US-20240321747-A1US-20220359679-A1US-12495587-B2, US-12494428-B2, and US-20240186374-A1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references disclose the limitations of the claims except for “a backside gate contact structure connected to a bottom surface of the gate structure in the backside isolation structure, wherein the backside gate contact structure is misaligned with the bottom surface of the gate structure to be closer to the 2nd source/drain region than the 1st source/drain region.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VU A VU/Primary Examiner, Art Unit 2897