Prosecution Insights
Last updated: April 19, 2026
Application No. 18/380,972

Display Module and Method for Manufacturing Display Module

Non-Final OA §102§103
Filed
Oct 17, 2023
Examiner
VU, VU A
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hudei Xinying Optoelectronics Co. Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 0m
To Grant
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
1208 granted / 1309 resolved
+24.3% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
48 currently pending
Career history
1357
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
44.5%
+4.5% vs TC avg
§102
34.4%
-5.6% vs TC avg
§112
12.5%
-27.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1309 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lou et al. (U.S. Patent No. 12,205,976). Regarding to claim 1, Lou teaches a display module comprising: a substrate (Fig. 2, Fig. 4, element 910; column 6, line 7), a plurality of pixel units are arrayed on the substrate (Fig. 2, elements 100; column 3, line 56), and each of the pixel units is provided with at least three light-emitting chips (Fig. 2, please see the attached figure, the three LE chips in each pixel), and centers of at least three light-emitting chips are not collinear (Fig 2, the three chips are not arranged in a line, instead they are arranged as triangle); and projections of at least three light-emitting chips along a first direction at least partially overlap, and projections of at least three light-emitting chips along a second direction at least partially overlap, wherein the first direction is perpendicular to the second direction (Fig. 2). PNG media_image1.png 513 833 media_image1.png Greyscale Regarding to claim 2, Lou teaches each of the pixel units is provided with three light-emitting chips, and lines connecting the centers of the three light-emitting chips form an acute-angled triangle (Fig. 2). PNG media_image2.png 502 463 media_image2.png Greyscale Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lou et al. (U.S. Patent No. 12,205,976), as applied to claim 1 above, in view of Peng (U.S. Patent Application Publication No. 2009/0191669). Regarding to claim 4, Lou discloses a surface of the substrate is covered with exposure glue, the exposure glue forms grooves on surfaces of the light-emitting chips (Fig. 4, element 930). Lou does not disclose the glue is dissolving glue, and the grooves are filled with colloids, colors of the colloids are basically the same as that of the exposure dissolving glue. Peng discloses a glue is dissolving glue, and the grooves are filled with colloids, colors of the colloids are basically the same as that of the exposure dissolving glue (Fig. 3, steps A-C, [0018], lines 1-10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fill the grooves with colloids, colors of the colloids are basically the same as that of the exposure dissolving glue, in order secure the light-emitting chips on precise positions on the substrate. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lou et al. (U.S. Patent No. 12,205,976) in view of Peng (U.S. Patent Application Publication No. 2009/0191669). Regarding to claim 6, Lou teaches a method for manufacturing a first display module, the method comprising: fixing at least three first light-emitting chips (Fig. 2, please see the attached figure, the three LE chips in each pixel) into one pixel unit (Fig. 2, element 100; column 3, line 56) of a first substrate so as to make centers of at least three first light-emitting chips not collinear (Fig. 2, the three chips are not arranged in a line, instead they are arranged as triangle), projections of at least three first light-emitting chips along a first direction at least partially overlap, and projections of at least three first light-emitting chips along a second direction at least partially overlap, wherein the first direction is perpendicular to the second direction (Fig. 2); covering a surface of the first substrate with exposure glue so as to make the exposure glue cover the first light-emitting chips (Fig. 4, element 930). Lou does not disclose the glue is dissolving glue, lighting up the first light-emitting chips, and dissolving the exposure dissolving glue at the corresponding positions of the first light-emitting chips. Peng discloses covering a surface of a substrate with exposure dissolving glue so as to make the exposure dissolving glue cover a chip, lighting up the chips and dissolving the exposure dissolving glue at the corresponding positions of the chip (Fig. 3, steps A-C, [0018], lines 1-10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lou in view of Peng to light up the first light-emitting chips, and dissolve the exposure dissolving glue at the corresponding positions of the first light-emitting chips, in order secure the light-emitting chips on precise positions on the substrate. Regarding to claim 7, Lou as modified discloses the exposure dissolving glue forms first grooves on the surfaces of the first light-emitting chips (Peng, Fig. 3, step A), after dissolving the exposure dissolving glue at the corresponding positions of the first light-emitting chips, filling first colloids into the grooves, wherein colors of the first colloids are basically the same as that of the exposure dissolving glue (Peng, Fig. 3, step B). PNG media_image1.png 513 833 media_image1.png Greyscale Allowable Subject Matter Claims 3, 5, and 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding to claim 3, the prior art fails to anticipate or render obvious the claimed limitations including “one side of the substrate is provided with at least one common A-pole pad and a plurality of B-pole pads in each of the pixel units, the A-poles of at least three light-emitting chips are electrically connected to the common A-pole pad, and the B-poles of the light-emitting chips are respectively electrically connected to the corresponding B-pole pads, wherein polarities of the A-poles and the B-poles are opposite; and another side of the substrate is provided with a common pin in each of the pixel units, and the common pin is electrically connected to the common A-pole pad” in combination with the limitations recited in claim 1. Regarding to claim 5, the prior art fails to anticipate or render obvious the claimed limitations including “the surfaces of the exposure dissolving glue and the colloids are covered with optical glue, and the surface of the optical glue is covered with a polarizer” in combination with the limitations recited in claim 1 and claim 4. Regarding to claim 8, the prior art fails to anticipate or render obvious the claimed limitations including “after filling the first colloids into the grooves, the method further comprising covering the surfaces of the first colloids and the exposure-dissolving glue with optical glue; and covering the surface of the optical glue with a polarizer” in combination with the limitations recited in claim 6 and claim 7. Regarding to claim 9, the prior art fails to anticipate or render obvious the claimed limitations including “fixing at least three second light-emitting chips to one pixel unit of a second substrate so as to make the second light-emitting chips in the same pixel unit and the first light-emitting chips of the first display module according to claim 6 mirror images of each other; covering a surface of the second substrate with exposure dissolving glue so as to make the exposure dissolving glue cover the second light-emitting chips; and aligning the first display module according to claim 6 with the second substrate so that the first light-emitting chips face the second light-emitting chips” in combination with the limitations recited in claim 6 and the rest of limitations recited in claim 9. Pertinent Art For the benefits of the Applicant, US-10763415-B2, US-11895888-B2, US-11545472-B2, US-20150077645-A1, US-11943986-B2, US-20230180551-A1, US-20180233492-A1, US-12185584-B2, and US-20100181582-A1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references disclose the claimed limitation except for covering a surface of the first substrate with exposure dissolving glue so as to make the exposure dissolving glue cover the first light-emitting chips; and lighting up the first light-emitting chips, and dissolving the exposure dissolving glue at the corresponding positions of the first light-emitting chips. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VU A VU/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Oct 17, 2023
Application Filed
Feb 24, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+6.6%)
2y 0m
Median Time to Grant
Low
PTA Risk
Based on 1309 resolved cases by this examiner. Grant probability derived from career allow rate.

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