DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-30 are objected to because of the following informalities:
Claim 1 recites “the first and second active layers” (lines 5 and 7) which should be replaced with “the first active layer and the second active layer”, for consistency with claim language.
Claim 23 recites “incudes” which should be replaced with “includes”, to correct claim language.
Claim 27 recites “the first and second active layers” (lines 7 and 9) which should be replaced with “the first active layer and the second active layer”, for consistency with claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 13, 24, 27, and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2016/0315104 to Han et al. (hereinafter Han).
With respect to claim 1, Han discloses a display panel (e.g., thin film transistor structure for display panel, see the annotated Figs. 3-4 and 6 below) (Han, Figs. 3-4, 6, ¶0006-¶0057) comprising:
a first active layer (e.g., SC2) (Han, Figs. 3-4, ¶0048) disposed on the substrate (1) and comprising a first channel region (e.g. under the top gate);
a second active layer (e.g., SC1) overlapping a portion of the first active layer (SC2), and comprising a second channel region (e.g. under the top gate) not overlapping the first channel region (SC2) of the first active layer;
first (S1/S2) (Han, Figs. 3-4, 6, ¶0048-¶0049) and second (D1/D2) electrodes disposed in respective portions of the first (SC2) and second (SC1) active layers, respectively, and spaced apart from each other;
a gate insulating layer (5/7) (Han, Figs. 4, 6, ¶0048) disposed in respective portions of upper surfaces of the first (SC2) and second (SC1) active layers; and
a third electrode (e.g., top electrode) (Han, Figs. 4, 6, ¶0048) disposed on the gate insulating layer (5/7),
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wherein the first channel region of the first active layer (SC2) and the second channel region of the second active layer (SC1) are connected (e.g., through the insulation layer 5) in parallel to each other.
Regarding claim 5, Han discloses the display panel of claim 1. Further, Han discloses the display panel, wherein a width of the first channel region (SC2) (Han, Figs. 3-4, 6, ¶0048-¶0049) is less than a width (e.g., under the top gate) of the gate insulating layer (5/7), and a width of the second channel region (SC1) is less than the width of the gate insulating layer (5/7).
Regarding claim 13, Han discloses the display panel of claim 1. Further, Han discloses the display panel, wherein the first channel region (SC2) (Han, Figs. 3-4, 6, ¶0048-¶0049) and the second channel region (SC1) are spaced apart from each other.
Regarding claim 24, Han discloses the display panel of claim 1. Further, Han discloses the display panel, wherein the gate insulating layer (5) is disposed on a portion of the first active layer (SC2) (Han, Fig. 4, ¶0048-¶0049) overlapping the second active layer (SC1), is disposed on a portion of the second active layer (SC1) (Han, Fig. 4) not overlapping the first active layer (SC2), and is disposed in a portion of an area not overlapping the first active layer (SC2) (Han, Fig. 4) among an area located under the first active layer (SC2).
With respect to claim 27, Han discloses a display device (see the annotated Figs. 3-4 and 6 above) (Han, Figs. 3-4, 6, ¶0006-¶0057) comprising:
a display panel and a driving circuit (e.g., AMOLED pixel compensation circuit) (Han, Figs. 3-4, 6, ¶0003-¶0006) configured to drive the display panel, wherein the display panel includes:
a first active layer (e.g., SC2) (Han, Figs. 3-4, ¶0048) disposed on the substrate (1) and comprising a first channel region (e.g. under the top gate);
a second active layer (e.g., SC1) overlapping a portion of the first active layer (SC2), and comprising a second channel region (e.g. under the top gate) not overlapping the first channel region (SC2) of the first active layer;
first (S1/S2) (Han, Figs. 3-4, 6, ¶0048-¶0049) and second (D1/D2) electrodes disposed in respective portions of the first (SC2) and second (SC1) active layers, respectively, and spaced apart from each other;
a gate insulating layer (5/7) (Han, Figs. 4, 6, ¶0048) disposed in respective portions of upper surfaces of the first (SC2) and second (SC1) active layers; and
a third electrode (e.g., top electrode) (Han, Figs. 4, 6, ¶0048) disposed on the gate insulating layer (5/7).
Regarding claim 28, Han discloses the display device of claim 27. Further, Han discloses display device, wherein the first channel region of the first active layer (SC2) (Han, Figs. 4, 6, ¶0048-¶0049) and the second channel region of the second active layer (SC1) are connected (e.g., through the insulation layer 5) in parallel to each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10-14, and 24-30 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0017992 to Jinbo in view of Kim et al. (US 2018/0350995, hereinafter Kim).
With respect to claim 1, Jinbo discloses a thin film transistor (e.g., see the annotated Fig. 1A below) (Jinbo, Figs. 1A-1B, 2, ¶0006, ¶0010-¶0019, ¶0044-¶0083) comprising:
a first active layer (e.g., 109a/109b) (Jinbo, Figs. 1A-1B, ¶0045-¶0050, ¶0075-¶0077) disposed on the substrate (100) and comprising a first channel region (e.g., a channel of the first/third transistor 101/103 with a channel length b/c);
a second active layer (e.g., 113) (Jinbo, Figs. 1A-1B, ¶0045, ¶0061-¶0063, ¶0075-¶0077) overlapping a portion of the first active layer (109a/109b), and comprising a second channel region (e.g., a channel of the second transistor 102 in the region a) not overlapping the first channel region (109a/109b) of the first active layer;
first (117a) (Jinbo, Figs. 1A-1B, ¶0045, ¶0072) and second (117b) electrodes disposed in respective portions of the first (109a/109b) and second (113) active layers, respectively, and spaced apart from each other;
a gate insulating layer (107a) (Jinbo, Figs. 1A-1B, ¶0045, ¶0068-¶0070) disposed in respective portions of the first (109a/109b) and second (113) active layers; and
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a third electrode (e.g., electrode 105) (Jinbo, Figs. 1A-1B, ¶0045, ¶0065-¶0067) disposed on the gate insulating layer (107a),
wherein the first channel region of the first active layer (109a/109b) and the second channel region of the second active layer (113) are connected (e.g., the first channel region b/c and the second channel region a are parallel to the substrate 100 and are connected to each other) (Jinbo, Figs. 1A, 2, ¶0077) in parallel to each other.
Further, Jinbo does not specifically disclose a display panel, wherein a gate insulating layer disposed in respective portions of upper surfaces of the first and second active layers.
However, Kim teaches forming a flat panel display device (Kim, Figs. 2-4, 20-21, ¶0013-¶0014, ¶0051-¶0059, ¶0144-¶0164) comprising a display panel (1100) (Kim, Figs. 2-4, 20-21, ¶0052-¶0053) including a thin film transistor (TFT) on a TFT substrate (1110), and configured in a coplanar structure as a top gate TFT (Kim, Figs. 2-4, 20-21, ¶0144-¶0160), wherein a gate insulating layer (120) disposed in respective portions of upper surfaces of the first and second active layers (131 and 132) (Kim, Figs. 2-4, 20-21, ¶0158-¶0160, ¶0086-¶0089).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thin film transistor of Jinbo by forming a top gate TFT with a coplanar structure on a TFT substrate of a display panel as taught by Kim to have a display panel, wherein a gate insulating layer disposed in respective portions of upper surfaces of the first and second active layers, in order to provide an improved flat panel display device which requires high-speed driving due to a high resolution (Kim, ¶0012-¶0014, ¶0145, ¶0164).
Regarding claim 2, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo in view of Kim discloses the display panel, wherein a material of the first active layer (e.g., microcrystalline semiconductor layers 109a/109b) (Jinbo, Figs. 1A-1B, ¶0045-¶0050) and a material of the second active layer (e.g., an amorphous semiconductor layer 113) (Jinbo, Figs. 1A-1B, ¶0045, ¶0061-¶0063) are different from each other, and a mobility of the first active layer and a mobility of the second active layer are different from each other (e.g., the increase in concentration of donors in the microcrystalline semiconductor layer 109a/109b leads to higher electric field effect mobility and the amorphous semiconductor layer 113 has lower concentration, and thus lower electric field effect mobility) (Jinbo, Figs. 1A-1B, ¶0006, ¶0019, ¶004- ¶0050, ¶0063).
Regarding claim 3, Jinbo in view of Kim discloses the display panel of claim 2. Further, Jinbo does not specifically disclose that each of the first active layer and the second active layer comprises at least one of Indium Zinc Oxide (IZO), Thin Transparent W-Doped Indium- ZincOxide (WIZO), Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Indium Gallium Tin Zinc Oxide (IGTZO), Zinc Oxide Nitride (ZnON), and Indium Gallium Oxide (IGO).
However, Kim teaches forming the first and second active layers (131 and 132) (Kim, Figs. 2-4, 20-21, ¶0089, ¶0091), wherein each of the first active layer (e.g., 131) and the second active layer (132) comprises at least one of Indium Gallium Zinc Oxide (IGZO), Indium Gallium Tin Zinc Oxide (IGTZO), wherein IGTZO has higher electron mobility than IGZO.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thin film transistor of Jinbo/Kim by forming a top gate TFT having oxide semiconductor channel layers having different electron mobilities as taught by Kim to have a display panel, wherein each of the first active layer and the second active layer comprises at least one of Gallium Zinc Oxide (IGZO), Indium Gallium Tin Zinc Oxide (IGTZO), in order to provide an improved flat panel display device which requires high-speed driving due to a high resolution (Kim, ¶0012-¶0014, ¶0145, ¶0164).
Regarding claim 4, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo in view of Kim discloses the display panel, wherein the second active layer (113) (Jinbo, Figs. 1A-1B, ¶0045, ¶0061-¶0063, ¶0075-¶0077) is disposed under the first active layer (e.g., in the region a), and the second active layer (113) except for the second channel region (e.g., in the region a) overlaps the first active layer (109a/109b).
Regarding claim 5, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo in view of Kim discloses the display panel, wherein a width of the first channel region (109a/109b) is less than a width of the gate insulating layer (107a) (Jinbo, Figs. 1A-1B, ¶0045, ¶0068-¶0070), and a width of the second channel region (113) is equal less than the width of the gate insulating layer (107a).
Regarding claim 6, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo in view of Kim discloses the display panel, wherein an area (e.g., in regions b/c) (Jinbo, Figs. 1A-1B, ¶0077) of the first active layer (109a/109b) (Jinbo, Figs. 1A-1B, ¶0045-¶0050, ¶0075-¶0077), except for areas overlapping the first electrode (117a), the second electrode (117b), and the third electrode (105), is a conductivity- enabled area (e.g., having a conductivity) (Jinbo, Figs. 1A-1B, ¶0049-¶0050).
Regarding claim 7, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo in view of Kim discloses the display panel, wherein: the first electrode (117a) (Jinbo, Figs. 1A-1B, ¶0045), the second electrode (117b), and the third electrode (105) spaced apart from each other are disposed on the substrate (100); the second active layer (113) is disposed (e.g., in a region a) (Jinbo, Figs. 1A-1B, ¶0077) under the first active layer (109a/109b) disposed under the first electrode (117a); the first active layer (109a/109b) and the second active layer (113) disposed under the first active layer are disposed in a portion of an area (e.g., regions b/a/c) between the first electrode (117a) and the third electrode (105); the first active layer (109a/109b) and the second active layer (113) disposed under the first active layer are disposed in a portion of an area (e.g., regions b/a/c) between the third electrode (105) and the second electrode (117b); the first active layer (109a/109b) and the second active layer (113) disposed under the first active layer are disposed under the second electrode (117b); the entire second channel region (e.g., region a) of the second active layer (113) overlaps a portion of the third electrode (105); and an area of the first active layer (109a/109b) disposed around the second channel region (e.g., region a) on the second active layer (113) and overlapping the third electrode (105) is at least a portion of a remaining area (e.g., outside region b and c) of the first active layer except for the first channel region.
Regarding claim 10, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo in view of Kim discloses the display panel, wherein the first active layer (109a/109b) (Jinbo, Figs. 1A-1B, ¶0045-¶0050, ¶0075-¶0077) comprises: a first portion (e.g., 109a, outside the region b) extending in a first direction (e.g., a horizontal direction in Fig. 1A) and overlapping the second active layer (113); a second portion (e.g., 109b, outside the region c) spaced apart from the first portion (109a), extending in the first direction (e.g., the horizontal direction in Fig. 1A), and overlapping the second active layer (113); and a third portion (e.g., regions b and c) disposed between the first portion e.g., 109a, outside the region b) and the second portion (e.g., 109b, outside the region c), overlapping the second active layer (113), and including the first channel region.
Regarding claim 11, Jinbo in view of Kim discloses the display panel of claim 10. Further, Jinbo in view of Kim discloses the display panel, wherein: the first electrode (117a) (Jinbo, Fig. 1B, ¶0044-¶0045, ¶0072, ¶0074) is disposed on a portion of the first portion (e.g., 109a, outside the region b); the second electrode (117b) is disposed on a portion of the second portion (e.g., 109b, outside the region c); and an entirety of each of the first electrode (117a, side surface of the second channel layer 113 in contact with the wiring 117a/117b, as in Fig. 1B) (Jinbo, Fig. 1B, ¶0074) and the second electrode (117b) overlaps the first active layer (109a/109b) and the second active layer (113).
Regarding claim 12, Jinbo in view of Kim discloses the display panel of claim 10. Further, Jinbo in view of Kim discloses the display panel, wherein the first channel region (e.g., regions b/c) (Jinbo, Fig. 1B, ¶0044-¶0045, ¶0077) of the first active layer (109a/109b) overlaps the second active layer (113), and the second channel region (e.g., region a) of the second active layer (113) does not overlap the first active layer (109a/109b).
Regarding claim 13, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo in view of Kim discloses the display panel, wherein the first channel region (e.g., regions b/c) (Jinbo, Fig. 1B, ¶0044-¶0045, ¶0077) and the second channel region (e.g., region a) are spaced apart from each other (e.g., occupied different spaces).
Regarding claim 30, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo does not specifically disclose that an area of the first channel region is about 1/3 to 3 times an area of the second channel region.
However, Jinbo teaches that on current and field effect mobility increase when the second channel region ("a") (Jinbo, Figs. 1A, 2, ¶0077) is shortened and the first channel region ("b/c") is lengthened, relative to the channel length L.
Thus, Jinbo recognizes that the sizes of the first channel and the second channel impact on current and field effect mobility of the thin film transistor. Thus, the sizes of the first channel and the second channel are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the sizes of the first channel and the second channel as Jinbo has identified the sizes of the first channel and the second channel as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific area of the first channel region and a specific area of the second channel region, in order to provide a desired on current and field effect mobility of the thin film transistor as taught by Jinbo (¶0077) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Jinbo/Kim by optimizing the sizes of the first channel and the second channel as taught by Jinbo to have a display panel, wherein an area of the first channel region is about 1/3 to 3 times an area of the second channel region, in order to provide a desired on current and field effect mobility, and to provide a thin film transistor capable of high-speed operation (Jinbo, ¶0010, ¶0077).
Regarding claim 24, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo in view of Kim discloses the display panel, wherein the gate insulating layer (107a) (Jinbo, Figs. 1A-1B, ¶0045, ¶0068-¶0070, ¶0077) is disposed on a portion of the first active layer (109a/109b) overlapping the second active layer (113), is disposed on a portion (e.g., in a region a and outside regions b and c) of the second active layer (113) not overlapping the first active layer (109a/109b), and is disposed in a portion of an area (e.g., region a) not overlapping the first active layer (109a/109b) among an area located under the first active layer (109a/109b).
Regarding claim 25, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo in view of Kim discloses the display panel, wherein the first active layer (109a/109b) Jinbo, Figs. 1A-1B, ¶0045, ¶0077) and the second active layer (113), which have respective channel regions (b/c and a) located in different areas, share one first electrode (117a), one second electrode (117b), and one third electrode (105).
Regarding claim 26, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo does not specifically disclose that the first and second channel regions include different oxide semiconductor materials.
However, Kim teaches forming the first and second active layers (131 and 132) (Kim, Figs. 2-4, 20-21, ¶0089, ¶0091), wherein each of the first active layer (e.g., 131) and the second active layer (132) comprises different oxide semiconductor materials (e.g., Indium Gallium Zinc Oxide (IGZO) and Indium Gallium Tin Zinc Oxide (IGTZO) have different electron mobilities), to provide a TFT including an oxide semiconductor layer capable of being applied to high-resolution flat panel display devices requiring high-speed driving.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thin film transistor of Jinbo/Kim by forming a top gate TFT having oxide semiconductor channel layers having different electron mobilities as taught by Kim to have a display panel, wherein the first and second channel regions include different oxide semiconductor materials, in order to provide an improved flat panel display device which requires high-speed driving due to a high resolution (Kim, ¶0012-¶0014, ¶0145, ¶0164).
With respect to claim 27, Jinbo discloses a thin film transistor (see the annotated Fig. 1A above) (Jinbo, Figs. 1A-1B, ¶0006, ¶0010-¶0019, ¶0044-¶0083) comprising:
a first active layer (e.g., 109a/109b) (Jinbo, Figs. 1A-1B, ¶0045-¶0050, ¶0075-¶0077) disposed on the substrate (100) and comprising a first channel region (e.g., a channel of the first/third transistor 101/103 with a channel length b/c);
a second active layer (e.g., 113) (Jinbo, Figs. 1A-1B, ¶0045, ¶0061-¶0063, ¶0075-¶0077) overlapping a portion of the first active layer (109a/109b), and comprising a second channel region (e.g., a channel of the second transistor 102 in the region a) not overlapping the first channel region (109a/109b) of the first active layer;
first (117a) (Jinbo, Figs. 1A-1B, ¶0045, ¶0072) and second (117b) electrodes disposed in respective portions of the first (109a/109b) and second (113) active layers, respectively, and spaced apart from each other;
a gate insulating layer (107a) (Jinbo, Figs. 1A-1B, ¶0045, ¶0068-¶0070) disposed in respective portions of the first (109a/109b) and second (113) active layers; and
a third electrode (e.g., electrode 105) (Jinbo, Figs. 1A-1B, ¶0045, ¶0065-¶0067) disposed on the gate insulating layer (107a).
Further, Jinbo does not specifically disclose a display device comprising: a display panel and a driving circuit configured to drive the display panel, wherein a gate insulating layer disposed in respective portions of upper surfaces of the first and second active layers.
However, Kim teaches forming a flat panel display device (Kim, Figs. 2-4, 20-21, ¶0013-¶0014, ¶0051-¶0059, ¶0144-¶0164) comprising a display panel (1100) (Kim, Figs. 2-4, 20-21, ¶0052-¶0053) including a thin film transistor (TFT) on a TFT substrate (1110), and configured in a coplanar structure as a top gate TFT (Kim, Figs. 2-4, 20-21, ¶0144-¶0160), wherein a gate insulating layer (120) disposed in respective portions of upper surfaces of the first and second active layers (131 and 132) (Kim, Figs. 2-4, 20-21, ¶0158-¶0160, ¶0086-¶0089).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thin film transistor of Jinbo by forming a top gate TFT with a coplanar structure on a TFT substrate of a display panel as taught by Kim to have a display device comprising: a display panel and a driving circuit configured to drive the display panel, wherein a gate insulating layer disposed in respective portions of upper surfaces of the first and second active layers, in order to provide an improved flat panel display device which requires high-speed driving due to a high resolution (Kim, ¶0012-¶0014, ¶0145, ¶0164).
Regarding claim 28, Jinbo in view of Kim discloses the display device of claim 27. Further, Jinbo in view of Kim discloses the display device, wherein the first channel region (e.g., regions b/c) of the first active layer (109a/109b) and the second channel region (e.g., region a) of the second active layer (113) are connected in parallel to each other (e.g., the first channel region b/c and the second channel region a are parallel to the substrate 100 and are connected to each other).
Regarding claim 29, Jinbo in view of Kim discloses the display device of claim 27. Further, Jinbo does not specifically disclose that the first and second channel regions include different oxide semiconductor materials.
However, Kim teaches forming the first and second active layers (131 and 132) (Kim, Figs. 2-4, 20-21, ¶0089, ¶0091), wherein each of the first active layer (e.g., 131) and the second active layer (132) comprises different oxide semiconductor materials (e.g., Indium Gallium Zinc Oxide (IGZO) and Indium Gallium Tin Zinc Oxide (IGTZO) have different electron mobilities), to provide a TFT including an oxide semiconductor layer capable of being applied to high-resolution flat panel display devices requiring high-speed driving.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Jinbo/Kim by forming a top gate TFT having oxide semiconductor channel layers having different electron mobilities as taught by Kim to have a display panel, wherein the first and second channel regions include different oxide semiconductor materials, in order to provide an improved flat panel display device which requires high-speed driving due to a high resolution (Kim, ¶0012-¶0014, ¶0145, ¶0164).
Regarding claim 30, Jinbo in view of Kim discloses the display device of claim 27. Further, Jinbo does not specifically disclose that a ratio of an area of the first channel region to an area of the second channel region is about 1:3 to 3:1.
However, Jinbo teaches that on current and field effect mobility increase when the second channel region ("a") (Jinbo, Figs. 1A, 2, ¶0077) is shortened and the first channel region ("b/c") is lengthened, relative to the channel length L.
Thus, Jinbo recognizes that the sizes of the first channel and the second channel impact on current and field effect mobility of the thin film transistor. Thus, the sizes of the first channel and the second channel are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the sizes of the first channel and the second channel as Jinbo has identified the sizes of the first channel and the second channel as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific ratio of an area of the first channel region to an area of the second channel region, in order to provide a desired on current and field effect mobility of the thin film transistor as taught by Jinbo (¶0077) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Jinbo/Kim by optimizing the sizes of the first channel and the second channel as taught by Jinbo to have a display panel, wherein a ratio of an area of the first channel region to an area of the second channel region is about 1:3 to 3:1, in order to provide a desired on current and field effect mobility, and to provide a thin film transistor capable of high-speed operation (Jinbo, ¶0010, ¶0077).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0017992 to Jinbo in view of Kim (US 2018/0350995) as applied to claim 1, and further in view of Yamazaki (US 2014/0264324, hereinafter Yamazaki’324).
Regarding claim 8, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo discloses the display panel, wherein the first active layer (109a/109b) (Jinbo, Figs. 1A-1B, ¶0045-¶0050, ¶0075-¶0077) comprises: a first portion (109a) extending in a first direction (e.g., a horizontal direction in Fig. 1A) and partially overlapping the second active layer (113); a second portion (109b) spaced apart from the first portion (109a), extending in the first direction (e.g., the horizontal direction in Fig. 1A), and partially overlapping the second active layer (113), but does not specifically disclose a third portion disposed between the first portion and the second portion, not overlapping the second active layer, and including the first channel region.
However, Yamazaki’324 teaches forming a transistor (Yamazaki’324, Figs. 7A-7C, ¶0006-¶0007, ¶0038-¶0087, ¶0159-¶0168) having high-speed operation and improved on-state characteristics, wherein the active layer (106) has a plurality of openings (Yamazaki’324, Figs. 7A-7C, ¶0040) in the channel width direction to define a plurality of channel formation regions including a third portion (e.g., 106b) disposed between the first portion and the second portion, not overlapping the second active layer (e.g., the n-type regions at the end portion of the active layer 106 in the channel length direction) (Yamazaki’324, Figs. 7A-7C, ¶0051-¶0052), and including the first channel region.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Jinbo/Kim by forming a plurality of openings in the channel width direction to define a plurality of channel formation regions as taught by Yamazaki’324 to have a display panel, wherein a third portion disposed between the first portion and the second portion, not overlapping the second active layer, and including the first channel region, in order to provide a transistor having high-speed operation and improved on-state characteristics (Yamazaki’324, ¶0006-¶0007, ¶0040, ¶0051-¶0052, ¶0168).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0017992 to Jinbo in view of Kim (US 2018/0350995) and Yamazaki’324 (US 2014/0264324) as applied to claim 8, and further in view of Tanaka et al. (US Patent No. 5,122,849, hereinafter Tanaka).
Regarding claim 9, Jinbo in view of Kim and Yamazaki’324 discloses the display panel of claim 8. Further, Jinbo discloses the display panel, wherein: the first electrode (117a) (Jinbo, Figs. 1A-1B, ¶0045, ¶0072) is disposed on a portion of the first portion; the second electrode (117b) is disposed on a portion of the second portion; each of the first electrode (117a) and the second electrode (177b) overlaps an area of the first active layer (109a/109b) disposed on the second active layer (113), but does not specifically disclose that each of the first electrode and the second electrode overlaps a portion of an area of the first active layer not overlapping the second active layer, and the third electrode overlaps the third portion of the first active layer.
However, Tanaka teaches forming a thin film transistor comprising the first active layer (4) (Tanaka, Figs. 3-4, Col. 1, lines 44-49; Col. 3, lines 49-68) that overlaps a second active layer (5), and forming each of the first electrode (7) and the second electrode (8) overlapping a portion of an area of the first active layer (4) not overlapping the second active layer (5), to improve performance characteristics of the thin film transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Jinbo/Kim/Yamazaki’324 by forming each of the first electrode and the second electrode overlapping a portion of an area of the first active layer not overlapping the second active layer as taught by Tanaka to have a display panel, wherein each of the first electrode and the second electrode overlaps a portion of an area of the first active layer not overlapping the second active layer, in order to improve performance characteristics of the thin film transistor (Tanaka, Col. 1, lines 44-49; Col. 4, lines 55-59).
Further, Yamazaki’324 teaches that the third electrode (e.g., gate electrode 116) (Yamazaki’324, Figs. 7A-7C, ¶0161) overlaps the third portion (106b) of the first active layer (106).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Jinbo/Kim/Yamazaki’324 by forming a plurality of openings in the channel width direction to define a plurality of channel formation regions under the gate electrode as taught by Yamazaki’324 to have a display panel, wherein the third electrode overlaps the third portion of the first active layer, in order to provide a transistor having high-speed operation and improved on-state characteristics (Yamazaki’324, ¶0006-¶0007, ¶0040, ¶0051-¶0052, ¶0168).
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0017992 to Jinbo in view of Kim (US 2018/0350995) as applied to claim 1, and further in view of Tanaka (US Patent No. 5,122,849).
Regarding claim 15, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo does not specifically disclose that the first active layer overlaps a plurality of second active layers.
However, Tanaka teaches forming a thin film transistor comprising the first active layer (4) (Tanaka, Figs. 9-10, Col. 1, lines 44-49; Col. 4, lines 43-67; Col. 5, lines 1-8) that overlaps a plurality of second active layers (5) arranged in a plurality of openings formed by a plurality of convex/concave parts of the first active layer (4), to improve performance characteristics of the thin film transistor (e.g., preventing lowering of the on-current).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Jinbo/Kim by forming a plurality of second active layers arranged in a plurality of openings formed by a plurality of convex/concave parts of the first active layer as taught by Tanaka to have a display panel, wherein the first active layer overlaps a plurality of second active layers, in order to improve performance characteristics of the thin film transistor (e.g., preventing lowering of the on-current) (Tanaka, Col. 1, lines 44-49; Col. 4, lines 55-59).
Regarding claim 16, Jinbo in view of Kim and Tanaka discloses the display panel of claim 15. Further, Jinbo does not specifically disclose that the plurality of second active layers are disposed spaced apart from each other under the first active layer, and each of the plurality of second active layers comprises a second channel region.
However, Jinbo teaches the second active layer (113) (Jinbo, Figs. 1A-1B, ¶0045, ¶0075-¶0077) disposed under the first active layer (109a/109b) in the channel region a in the opening of the first active layer (109a/109b).
Further, Tanaka teaches forming the plurality of second active layers (5) (Tanaka, Figs. 9-10, Col. 1, lines 44-49; Col. 4, lines 43-67; Col. 5, lines 1-8) arranged in a plurality of openings formed by a plurality of convex/concave parts of the first active layer (4) along the gate (2), and disposed spaced apart from each other, wherein each of the plurality of second active layers (5) comprises a channel region, to improve performance characteristics of the thin film transistor (e.g., preventing lowering of the on-current).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Jinbo/Kim/Tanaka by forming a plurality of second active layers arranged in a plurality of openings formed by a plurality of convex/concave parts of the first active layer as taught by Tanaka, wherein each of the plurality of second active layers is disposed under the first active layer as taught by Jinbo to have a display panel, wherein the plurality of second active layers are disposed spaced apart from each other under the first active layer, and each of the plurality of second active layers comprises a second channel region, in order to improve performance characteristics of the thin film transistor (e.g., preventing lowering of the on-current); and to obtain the thin film transistor capable of high-speed operation (Tanaka, Col. 1, lines 44-49; Col. 4, lines 55-59; Jinbo, ¶0010, ¶0077, ¶0081).
Regarding claim 17, Jinbo in view of Kim and Tanaka discloses the display panel of claim 16. Further, Jinbo does not specifically disclose that the first channel region of the first active layer is disposed between the plurality of second channel regions.
However, Tanaka teaches forming the plurality of second active layers (5) arranged in a plurality of openings formed by a plurality of convex/concave parts of the first active layer (4) (Tanaka, Figs. 9-10, Col. 1, lines 44-49; Col. 4, lines 43-67; Col. 5, lines 1-8) along the gate (2), such that the concave portions of the first active layer (4) are disposed between the plurality of second channel regions (5) formed in the convex portions of the first active layer (4), to improve performance characteristics of the thin film transistor (e.g., preventing lowering of the on-current).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Jinbo/Kim/Tanaka by forming a plurality of second active layers arranged in a plurality of openings formed by a plurality of convex/concave parts of the first active layer as taught by Tanaka to have a display panel, wherein the first channel region of the first active layer is disposed between the plurality of second channel regions, in order to improve performance characteristics of the thin film transistor (e.g., preventing lowering of the on-current) (Tanaka, Col. 1, lines 44-49; Col. 4, lines 55-59).
Regarding claim 18, Jinbo in view of Kim and Tanaka discloses the display panel of claim 16. Further, Jinbo discloses the display panel, wherein the first active layer (109a/109b) (JInbo, Figs. 1A-1B, ¶0007, ¶0010, ¶0045, ¶0077) and the second active layer (113) are used to form a transistor for a drive circuit, but does not specifically disclose that the plurality of second active layers are disposed in a gate driving circuit.
However, Tanaka teaches forming a thin film transistor comprising (Tanaka, Figs. 9-10, Col. 1, lines 44-49; Col. 4, lines 43-67; Col. 5, lines 1-8) the plurality of second active layers (5) arranged in a plurality of openings formed by a plurality of convex/concave parts of the first active layer (4), to improve performance characteristics of the thin film transistor (e.g., preventing lowering of the on-current).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Jinbo/Kim/Tanaka by forming a thin film transistor comprising the plurality of second active layers arranged in the plurality of openings formed by a plurality of convex/concave parts of the first active layer as taught by Tanaka, wherein the thin film transistor is used for the driver circuit as taught by Jinbo to have a display panel, wherein the plurality of second active layers are disposed in a gate driving circuit, in order to improve performance characteristics of the thin film transistor (e.g., preventing lowering of the on-current); and to obtain the thin film transistor capable of high-speed operation (Tanaka, Col. 1, lines 44-49; Col. 4, lines 55-59; Jinbo, ¶0010, ¶0077, ¶0081).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0017992 to Jinbo in view of Kim (US 2018/0350995) as applied to claim 1, and further in view of Jeon et al. (US 2021/0320162, hereinafter Jeon).
Regarding claims 19 and 20, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo does not specifically disclose the display panel, further comprising: at least one insulating layer disposed on the first electrode, the second electrode, and the third electrode; and an anode electrode disposed on the at least one insulating layer, wherein the anode electrode is electrically connected to the first electrode or the second electrode through a contact hole formed in the at least one insulating layer (as claimed in claim 19); wherein the anode electrode extends to a light emitting area, and in the light emitting area, an emission layer and a cathode electrode disposed on the emission layer are disposed on the anode electrode (as claimed in claim 20).
However, Jeon teaches forming a display panel (Jeon, Fig. 6, ¶0006-¶0007, ¶0032-¶0034, ¶0038-¶0082, ¶0100-¶0130) comprising pixels each having a light emission area (EA) (Jeon, Fig. 6, ¶0061) and a circuit area (CA) including a thin film transistor (TR1) connected to the light emitting element (OLED) in the light emission area (EA), wherein at least one insulating layer (e.g., PVX/VIA) (Jeon, Fig. 6, ¶0114-¶0120) disposed on the thin film transistor (TR1); and an anode electrode (151) disposed on the at least one insulating layer (PVX/VIA), wherein the anode electrode (151) is electrically connected to the source/drain region (131b) through a contact hole (CNT2) formed in the at least one insulating layer (PVX/VIA); wherein the anode electrode (151) extends to a light emitting area (EA), and in the light emitting area, an emission layer (EL) and a cathode electrode (CAT) (Jeon, Fig. 6, ¶0128) disposed on the emission layer (EL) are disposed on the anode electrode (151), to provide a display device capable of suppressing/preventing parasitic capacitors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Jinbo/Kim by forming a display device comprising a light emission area and a circuit area including a thin film transistor as taught by Jeon, wherein the thin film transistor including the first electrode and the second electrode as taught by Jinbo to have a display panel, further comprising: at least one insulating layer disposed on the first electrode, the second electrode, and the third electrode; and an anode electrode disposed on the at least one insulating layer, wherein the anode electrode is electrically connected to the first electrode or the second electrode through a contact hole formed in the at least one insulating layer (as claimed in claim 19); wherein the anode electrode extends to a light emitting area, and in the light emitting area, an emission layer and a cathode electrode disposed on the emission layer are disposed on the anode electrode (as claimed in claim 20), in order to provide a display device capable of suppressing/preventing parasitic capacitors); and to obtain the thin film transistor capable of high-speed operation (Jeon, ¶0006-¶0007, ¶0039, ¶0054, ¶0057, ¶0061; Jinbo, ¶0010, ¶0077, ¶0081).
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0017992 to Jinbo in view of Kim (US 2018/0350995) as applied to claim 1, and further in view of Feng et al. (US 2020/0119120, hereinafter Feng).
Regarding claims 21 and 22, Jinbo in view of Kim discloses the display panel of claim 1. Further, Jinbo does not specifically disclose the display panel, further comprising: a light shield disposed under the second active layer, wherein the light shield forms a storage capacitor by overlapping a first storage capacitor electrode disposed on a same layer as the first active layer and a second storage capacitor electrode disposed on a same layer as the first to third electrodes (as claimed in claim 21); wherein an entire area of the first and second channel
regions overlaps the light shield (as claimed in claim 22).
However, Kim teaches forming a light shield (Kim, Figs. 20-21, ¶0149-¶0150) disposed under the semiconductor layer (130) including the second active layer (132).
Further, Feng teaches forming a display unit (Feng, Fig. 2A, ¶0004-¶0009, ¶0049-¶0052, ¶0055-¶0082, ¶0100-¶0130) comprising a thin film transistor and a storage capacitor, wherein the thin film transistor is configured as a top gate structure including a plurality of insulating layers between the conductive layers to incorporate a storage capacitor with a large capacitance in a limited area in the pixel unit to meet the display requirements of the high PPI (pixel per inch), wherein a light shield (20) disposed under the active layer (A1) of the thin film transistor, and the light shield (19) forms a storage capacitor by overlapping a first storage capacitor electrode (11) disposed on a same layer as the active layer (A1) (Feng, Fig. 2A, ¶0061) and a second storage capacitor electrode (12) disposed on a same layer as the gate electrode (G1), and wherein an entire area of the channel region of the thin film transistor overlaps the light shield (20).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display panel of Jinbo/Kim by forming a pixel unit comprising a thin film transistor including a light shield as taught by Feng, wherein the thin film transistor is configured as a top gate structure including a light shield disposed under the semiconductor layer including a first active layer and a second active layer as taught by Kim to have a display panel, further comprising: a light shield disposed under the second active layer, wherein the light shield forms a storage capacitor by overlapping a first storage capacitor electrode disposed on a same layer as the first active layer and a second storage capacitor electrode disposed on a same layer as the first to third electrodes (as claimed in claim 21); wherein an entire area of the first and second channel regions overlaps the light shield (as claimed in claim 22), in order to protect the semiconductor layer of the thin film transistor by blocking light incident on the semiconductor layer; and to provide a storage capacitor with a large capacitance in a limited area in the pixel unit to meet the display requirements of the high PPI (pixel per inch) (Kim, ¶0150; Feng, ¶0049, ¶0052, ¶0061-¶0062).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0017992 to Jinbo in view of Kim (US 2018/0350995) as applied to claim 3, and further in view of Yamazaki et al. (US 2013/0009219, hereinafter Yamazaki) and Kikuchi et al. (US 2019/0280126, hereinafter Kikuchi).
Regarding claim 23, Jinbo in view of Kim discloses the display panel of claim 3. Further, Jinbo does not specifically disclose the display panel, wherein the first active layer includes indium zinc oxide, and an indium content of the first active layer is about 50% to 70%, and wherein the second active layer incudes indium gallium zinc oxide, and an indium content of the second active layer is from about 75% or more to less than 100%.
However, Yamazaki teaches forming a thin film transistor (Yamazaki, Fig. 1A, ¶0012-¶0022, ¶0077-¶0089) having increased on-state characteristics (e.g., on-state current and field-effect mobility) to provide high-speed response and high-speed operation of a semiconductor device, wherein an active semiconductor layer includes an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other. By using the oxide semiconductor stacked layer using a plurality of oxide semiconductor layers having different energy gaps, the electrical characteristics of the transistor can be adjusted with higher accuracy, providing the transistor with appropriate electrical characteristics.
The transistor (440a) (Yamazaki, Figs. 1A-1B, ¶0089-¶0091) includes the first active layer (101/102) composed of indium zinc oxide (e.g., In-Sn-Zn-based oxide) with energy band gap of 2.6 eV-2.8 eV and the second active layer (102/101) composed of indium gallium zinc oxide (e.g., In-Ga-Zn-based oxide) with energy band gap of 3.0 eV-3.2 eV.
Further, Kikuchi teaches forming an oxide semiconductor thin film transistor (Kikuchi, Figs. 1A-1B, ¶0008-¶0012, ¶0049-¶0091) comprising semiconductor active layer having layered structure, wherein the lower oxide semiconductor layer (71) has a high mobility material to realize high TFT mobility and improve ON characteristics, and atomic ratio of indium (In) with respect to all metal elements of the lower oxide semiconductor layer (71, In-Ga-Zn-Sn-O) (Kikuchi, Figs. 1A-1B, ¶0049) is higher than the atomic ratio of In with respect to all metal elements of the upper oxide semiconductor layer (72, In-Ga-Zn-O) to increase mobility of the oxide semiconductor layer (71). Specifically, the In ratio of the lower oxide semiconductor layer (71) (Kikuchi, Figs. 1A-1B, ¶0084) is between 25% and 45%, and the gallium (Ga) ratio of the lower oxide semiconductor layer (71) is between 5% and 20%, the In ratio may be greater than 2.0 times the Ga ratio ([In]/[Ga]>2.0), to realize a higher mobility.
Thus, Kikuchi recognizes that the In ratio of the first and second channel layers impacts ON characteristics and mobility of the thin film transistor. Thus, the In ratio of the first and second channel layers is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the In ratio of the the first and second channel layers as Kikuchi has identified the In ratio of the first and second channel layer as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific In ratio of the first and second channel layers, in order to provide improved ON characteristics and increased mobility of the thin film transistor as taught by Kikuchi (¶0049, ¶0084) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Jinbo/Kim by optimizing the In ratio of the first channel and the second channel layers with respect to all metal elements as taught by Kikuchi, wherein the first channel and the second channel layers have energy gaps different from each other as taught by Yamazaki to have a display panel, wherein the first active layer includes indium zinc oxide, and an indium content of the first active layer is about 50% to 70%, and wherein the second active layer incudes indium gallium zinc oxide, and an indium content of the second active layer is from about 75% or more to less than 100%, in order to provide high TFT mobility and improve ON characteristics; and to provide high-speed response and high-speed operation of a semiconductor device by adjusting electrical characteristics of the transistor (Kikuchi, ¶0008-¶0012, ¶0049, ¶0084; Yamazaki, ¶0008, ¶0012, ¶0022-¶0023, ¶0089-¶0091).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891