DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: (a) the second three-dimensional conductive layer 32. See applicants’ specification, page 9, paragraph 28, lines 10-11 . (b) insulation sealant 5. See id. , page 10, paragraph 31, line 3 . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: (a) In Figure 6: 120’, 124’; (b) In Figure 8, 1”, 30”, 32”, 34”, 320”; (c) In Figure 9, all reference numbers. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to because of the following: Figure 1: Delete “Figure” at the top of the sheet. Figures 8 and 9: It is unclear how Figure 9 is a plan view of Figure 8, if that is what is intended. In Figure 11: Second to last line in step (62): Check the translation of “further”. The current translation is awkward. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: Page 9, paragraph 28, line 23: Change “drain” to “gate”. Appropriate correction is required. Claim Objections Claims 1-8 are objected to because of the following informalities: Claim 1, line 8: Change “tires” to “tiers”. Compare with line 15. Claims 2-6 are objected to for depending from objected-to base claim 1. Claim 7, line 11: Change “second second ” to “second”. Claim 8 is objected to for depending from objected-to base claim 7. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1: This claim includes the following language: each of the at least one power transistor die being formed with a plurality of electrodes, each of the plurality of electrodes being electrically conductively connected to the first three-dimensional conductive layer or the second three-dimensional conductive layer, respectively , …. Claim 1 (emphasis added). The term “respectively” is typically used with two lists of an equal number of items, the term assigning one item from the first list to another item of the second list in the order of the listings. (Compare with claim 1, lines 20-23.) Here, there is “each of the plurality of electrodes” connected to either the first three-dimensional conductive layer or the second three-dimensional conductive layer . In the context of this claim language, the term “respectively” does not make sense. Because the term does not make sense, claim 1 is rejected as indefinite. Claims 2-6 are rejected for depending from rejected base claim 1. Regarding claim 3, which depends from claim 1: This claim includes the following language: “ wherein the first ceramic insulation layer and the second ceramic insulation layer have a thickness ranging from 0.1 mm to 1 mm, respectively . ” (emphasis added). As discussed above, the term “respectively” is typically used with two lists of an equal number of items, the term assigning one item from the first list to another item of the second list in the order of the listings. Here, there are two items in one list, the first ceramic insulation layer and the second ceramic insulation layer , and then a range. In the context of this claim language, the term “respectively” does not make sense. Because the term does not make sense, claim 3 is rejected as indefinite. Regarding claim 7: This claim, directed to a method, defines the power module in detail before defining the steps for making the power module. However, lines 17-18 require the following: “ forming a circuit on the first three-dimensional conductive layer, the first three-dimensional conductive layer being formed with a plurality of tiers of different heights ….” This language does not make sense because the circuit is formed on the first ceramic insulation layer to form the three-dimensional conductive layer, not on an already existing three-dimensional conductive layer to form (again) the three-dimensional conductive layer. Compare with claim 1, lines 6-8. Because this step does not make sense, claim 7 is rejected as indefinite. Claim 8 is rejected for depending from rejected base claim 7. Regarding claim 8, which depends from claim 7: This claim is rejected on two bases. First, the claim requires the following: “ wherein the forming a circuit on the first three-dimensional conductive layer further comprises: forming a seed layer on the first and second ceramic insulation layers, respectively; and forming a plurality of thickened layers sequentially on the seed layer .” The forming of the circuit on the first three-dimensional conductive layer relates to the first three-dimensional conductive layer formed on the first ceramic insulation layer, not to the second ceramic insulation layer. Because this language does not make sense with respect to the second ceramic insulation layer, claim 8 is rejected as indefinite. Second, the claim refers to forming a seed layer of the first and second ceramic insulation layers, respectively. As discussed above, the term “respectively” is typically used with two lists of an equal number of items, the term assigning one item from the first list to another item of the second list in the order of the listings. Here, there is one item, the seed layer, in one list, and two items, the first and second ceramic insulation layers, in the second list. Because the use of the term “respectively” does not make sense in the context of this claim, claim 8 is rejected as indefinite. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 , 2, and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo, U.S. Pat. Pub. No. 2021/0111104 , Figures 1-3 , and further in view of Shibuya, U.S. Pat. No. 9,620,440, Figures 3-6. Regarding claim 1 : Yoo Figure s 1 -3 disclose a heat-electricity discrete power module (2) including two-way heat-dissipation ceramic substrates (14, 68) , comprising: a first double-sided metal-clad ceramic substrate (18, 50, 14, 12) comprising a first ceramic insulation layer (14) , a first three-dimensional conductive layer (18, 50) formed on the first ceramic insulation layer (14) , and a first thermally-conductive metallic layer (12) which is formed on the first ceramic insulation layer (14) opposite the first three-dimensional conductive layer (18, 50) and insulated from the first three-dimensional conductive layer (18, 50) , wherein the first three-dimensional conductive layer (18, 50) is formed with a plurality of ti ers of different heights; a second double-sided metal-clad ceramic substrate (66, 68, 70) disposed parallel to the first double-sided metal-clad ceramic substrate (18, 50, 14, 12) , comprising a second ceramic insulation layer (68) , a second three-dimensional conductive layer (66) formed on the second ceramic insulation layer (68) , and a second thermally-conductive metallic layer (70) which is formed on the second ceramic insulation layer (68) opposite the second three-dimensional conductive layer (66) and insulated from the second three-dimensional conductive layer (66) ; and at least one power transistor die (4) , each of the at least one power transistor die (4) being formed with a plurality of electrodes (inherently present) , each of the plurality of electrodes being electrically conductively connected to the first three-dimensional conductive layer (19, 50) or the second three-dimensional conductive layer (66) , respectively, and an upper surface and a lower surface of the each of the at least one power transistor die (4) being thermally conductively connected to the first three-dimensional conductive layer (12) and the second three-dimensional conductive layer (70) , respectively. Yoo specification ¶¶ 42-46, 50-55. Yoo does not disclose that the second three-dimensional conductive layer (66) is formed with a plurality of tiers of different heights . Shibuya Figures 3-6, directed to similar subject matter, discloses a lead frame used in a power module, in which the first and second leadframes (320, 324; 310, 314 ) are three-dimensional conductive layers. Shibuya specification, col. 3, ll. 1-63. One having ordinary skill in the art would be motivated to modify Yoo to include the Shibuya design in the second three-dimensional conductive layer (66) because the modification would have involved the substitution of an equivalent known for the same purpose. Once modified, Yoo discloses the second three-dimensional conductive layer (66) is formed with a plurality of tiers of different heights . Regarding claim 2, which depends from claim 1: The combination discloses an insulation sealant (see Shibuya Figure 6) configured to completely encapsulate the at least one power transistor die interposed between the first and second double-sided metal-clad ceramic substrates. Shibuya specification, col. 3, ll. 55-63. Regarding claim 5, which depends from claim 1: The combination discloses a gate driver (present as required for contact, per Shibuya Figure 2) , the gate driver being mounted at the first three-dimensional conductive layer (Yoo: 18, 50) or the second three-dimensional conductive layer (Yoo: 66, as modified by Shibuya) and being configured to drive the at least one power transistor die (Yoo: 4) . Shibuya specification, col. 2, ll. 53-67; col. 3, ll. 1-11. Regarding claim 6, which depends from claim 1: The combination discloses at least one conductive post (Shibuya, 314 or 324, at left in Figures 3, 4; Yoo, 50/54 , at right in Figure 1) is formed between the first three-dimensional conductive layer (Yoo: 18, 50) and the second three-dimensional conductive layer (Yoo: 66, as modifed by Shibuya) . Yoo specification ¶¶ 50, 51. Regarding claim 7: Yoo discloses a manufacturing method of a heat-electricity discrete power module (2) including two-way heat-dissipation ceramic substrates (14, 68) , the heat-electricity discrete power module (2) including two-way heat-dissipation ceramic substrates (14, 68) comprising a first double-sided metal-clad ceramic substrate (18, 50, 14, 12) and a second double-sided metal-clad ceramic substrate (66, 69, 70) disposed parallel to the first double-sided metal-clad ceramic substrate (18, 50, 14, 12) , wherein the first double-sided metal-clad ceramic substrate (18, 50, 14, 12) comprises a first ceramic insulation layer (14) , a first three-dimensional conductive layer (18, 50) formed on the first ceramic insulation layer (14) , and a first thermally-conductive metallic layer (12) which is formed on the first ceramic insulation layer (14) opposite the first three-dimensional conductive layer (18, 50) a nd insulated from the first three-dimensional conductive layer (18, 50) ; and the second […] double-sided metal-clad ceramic substrate (66, 68, 70) comprises a second ceramic insulation layer (68) , a second three-dimensional conductive layer (66) formed on the second ceramic insulation layer (68) , and a second thermally-conductive metallic layer (70) which is formed on the second ceramic insulation layer (68) opposite the second three-dimensional conductive layer (66) and insulated from the second three-dimensional conductive layer (66) ; the manufacturing method comprises: forming a circuit (50) on the first three-dimensional conductive layer (18, 50) , the first three-dimensional conductive layer (18, 50) being formed with a plurality of tiers of different heights; mounting at least one power transistor die (4) at the circuit (50) of the first double-sided metal-clad ceramic substrate (18, 50, 14, 12) , so that the at least one power transistor die (4) is thermally conductively connected to the first three-dimensional conductive layer (18, 50, 14, 12) ; thermally conductively bonding the second double-sided metal-clad ceramic substrate (66, 68, 70) to the at least one power transistor die (4) in a manner that the second three-dimensional conductive layer (66) faces the at least one power transistor die (4). Yoo specification ¶¶ 42-46, 50-55. Yoo does not disclose potting an insulation sealant to completely encapsulate the at least one power transistor die . Shibuya, Figures 3-6, directed to similar subject matter, disclose potting an insulation sealant to completely encapsulate the at least one power transistor die (301) . Shibuya specification, col. 3, ll. 55-63. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Yoo to include the Shibuya step because the molding would protect and package the dies. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo and Shibuya , and further in view of Yoo Figure 5. Regarding claim 4, which depends from claim 1: The combination is directed to a single clip which packages the dies. Yoo Figure 5 discloses the at least one power transistor die (4) refers to an even number (twelve) of power transistor dies (4) which are divided into at least two groups (four groups) of power transistor dies (4) , the at least two groups (four groups) being serially connected to each other, the power transistor dies (4) in each of the at least two groups (four groups) being parallel connected to each other. Yoo specification ¶ 56. One having ordinary skill in the art would be motivated to modify the combination to place the combination in Yoo Figure 5 because the modification would have involved the substitution of an equivalent known for the same purpose. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo and Shibuya, and further in view of Jeun, U.S. Pat. No. 10,720,376, Figure 1. Regarding claim 3, which depends from claim 1: The combination is silent as to the thickness of the ceramic insulation layers. Jeun Figure 1, directed to a package in which a die is provided on a ceramic insulation substrate (1) with two metallized surfaces (3, 4), discloses its ceramic insulation layer (2) has a thickness of 0.630 mm. Jeun specification, col. 4, ll. 25-46. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Jeun thickness because the Jeun thickness is suitable for the intended use. Once combined, the combination discloses the first ceramic insulation layer and the second ceramic insulation layer have a thickness ranging from 0.1 mm to 1 mm, respectively. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo and Shibuya , and further in view of Yu, U.S. Pat. Pub. No. 2020/0245456, Figure 2. Regarding claim 8, which depends from claim 7: The combination is silent as to whether the step of the forming a circuit on the first three-dimensional conductive layer further comprises: forming a seed layer on the first and second ceramic insulation layers, respectively; and forming a plurality of thickened layers sequentially on the seed layer. Yu Figure 2, directed to similar subject matter, discloses the forming a circuit on the first three-dimensional conductive layer further comprises: forming a seed layer (232) on a ceramic insulation layer (21) ; and forming a plurality of thickened layers (231) sequentially on the seed layer (232) . Yu specification ¶ 22. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Yu step because the Yu step is suitable for forming the conductive layer. Once combined, the combination discloses that the step of the forming a circuit on the first three-dimensional conductive layer further comprises: forming a seed layer on the first and second ceramic insulation layers, respectively; and forming a plurality of thickened layers sequentially on the seed layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT VICTORIA KATHLEEN HALL whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7567 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday, 8 a.m.-5 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Fernando Toledo can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-1867 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Victoria K. Hall/ Primary Examiner, Art Unit 2897