DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 & 5-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20140291758).
Regrading claim 1, Lee discloses that an integrated circuit (IC) device, comprising:
a substrate 100 having a first gate trench GA and a second gate trench CA spaced apart from the first gate trench in a horizontal direction (Fig. 3J);
a gate dielectric layer 221G/221C covering inner surfaces of the first gate trench and the second gate trench (Fig. 3E);
a first lower gate electrode 223G filling a portion of the first gate trench on the gate dielectric layer 221G;
a second lower gate electrode 221C filling a portion of the second gate trench on the gate dielectric layer 221C;
a first upper gate electrode 233G on the first lower gate electrode 223G in the first gate trench and having a first width in the horizontal direction (Fig. 3I); and
a second upper gate electrode 233C on the second lower gate electrode 221C in the second gate trench and having a second width smaller than the first width (Fig. 3H, para. 0063), wherein a vertical level of an upper surface of the first upper gate electrode 233G is higher than or substantially equal to a vertical level of an upper surface of the second upper gate electrode 223C (Fig. 3I).
Reclaim 2, Lee discloses that a depth of the first gate trench GA in a vertical direction is greater than a depth of the second gate trench CA in the vertical direction (Fig. 3I).
Reclaim 3, Lee discloses that the upper surfaces of the first upper gate electrode and the second upper gate electrode are flat (Fig. 3I).
Reclaim 5, Lee discloses that an uppermost end of a sidewall of the first upper gate electrode contacting the gate dielectric layer has a vertical level substantially equal to an uppermost surface of the first upper gate electrode, and an uppermost end of a sidewall of the second upper gate electrode contacting the gate dielectric layer has a vertical level substantially equal to an uppermost surface of the second upper gate electrode (Fig. 3K).
Reclaim 6, Lee discloses that a vertical level of a lower surface of the first upper gate electrode is substantially equal to a vertical level of a lower surface of the second upper gate electrode (Fig. 3K).
Reclaim 7, Lee discloses that a first insulating capping layer 251G/252p on the first upper gate electrode in the first gate trench; and
a second insulating capping layer 251C/252pon the second upper gate electrode in the second gate trench and having a width smaller than a width of the first insulating capping layer, wherein a vertical level of a lower surface of the first insulating capping layer is higher than or substantially equal to a vertical level of a lower surface of the second insulating capping layer (Fig. 3K).
Reclaim 8, Lee discloses that the lower surface of the first insulating capping layer and the lower surface of the second insulating capping layer are flat (Fig. 3K).
Reclaim 9, Lee discloses that a first blocking layer 252p covering at least a portion of the upper surface of the first upper gate electrode, wherein a lower surface of the first blocking layer is flat (Fig. 3K).
Reclaim 10, Lee discloses that a second blocking layer 252p covering at least a portion of the upper surface of the second upper gate electrode, wherein a vertical level of the lower surface of the second blocking layer is lower than or substantially equal to a vertical level of the lower surface of the first blocking layer, and the lower surface of the second blocking layer is flat (Fig. 3K).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20140291758) in view of Jeong (US 20150187899).
Reclaim 4, Lee discloses that the first upper gate electrode and the second upper gate electrode include doped polysilicon, and the first lower gate electrode (para. 0047) and the second lower gate electrode. (Fig. 3I).
Lee fails to specify that the second lower gate electrode includes Ti, TiN, Ta TaN, W, Wn TiSiN. Or WSiN.
However, suggests that a lower gate electrode can be Ti, TiN, Ta TaN, W, Wn TiSiN. Or WSiN (para. 0032).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Lee with a lower gate electrode can be Ti, TiN, Ta TaN, W, Wn TiSiN. Or WSiN as taught by Jeong in order to enhance material variation and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Claim(s) 11-18 & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20140291758) in view of Grivna (US 20110136310).
Regarding claim 11, Lee discloses that an integrated circuit (IC) device, comprising:
a substrate 100 having a first gate trench GA and a second gate trench CA apart from the first gate trench in a horizontal direction;
a gate dielectric layer 221G/221C covering inner surfaces of the first gate trench GA and the second gate trench CA (Fig. 3E) ;
a first lower gate electrode 223G filling a portion of the first gate trench on the gate dielectric layer 221G;
a second lower gate electrode 223C filling a portion of the second gate trench on the gate dielectric layer 221C;
a first upper gate electrode 233G on the first lower gate electrode 2in the first gate trench; and
a second upper gate electrode 233C on the second lower gate electrode 223C in the second gate trench, wherein a vertical level of an upper surface of the first upper gate electrode 233G is higher than or substantially equal to a vertical level of an upper surface of the second upper gate electrode 233C.
Lee fails to teach that the upper surfaces of the first upper gate electrode and the second upper gate electrode have an upwardly convex rounded profile, and wherein the upwardly convex rounded profile contacts the inner surfaces of the first gate trench and the second gate trench.
However, Grivna suggests that a gate electrode 578 have an upwardly convex rounded profile, and wherein the upwardly convex rounded profile contacts the inner surfaces of the first gate trench and the second gate trench (Fig. 22).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Lee with the upper surfaces of the first upper gate electrode and the second upper gate electrode have an upwardly convex rounded profile, and wherein the upwardly convex rounded profile contacts the inner surfaces of the first gate trench and the second gate trench as taught by improves device performance (para. 0058) in order to Grivna and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 12, Lee & Grivna disclose that a first width of the first gate trench in the horizontal direction is greater than a second width of the second gate trench in the horizontal direction (Lee in view of Grivna).
Reclaim 13, Lee & Grivna disclose that an uppermost end of a sidewall of the first upper gate electrode contacting the gate dielectric layer has a vertical level lower than an uppermost surface of the first upper gate electrode, and an uppermost end of a sidewall of the second upper gate electrode contacting the gate dielectric layer has a vertical level lower than an uppermost surface of the second upper gate electrode (Lee in view of Grivna).
Reclaim 14. , Lee & Grivna disclose that a first insulating capping layer on the first upper gate electrode; and a second insulating capping layer on the second upper gate electrode, wherein a vertical level of a lower surface of the first insulating capping layer is higher than or substantially equal to a vertical level of a lower surface of the second insulating capping layer (Lee in view of Grivna).
Reclaim 15, Lee & Grivna disclose that the lower surface of the first insulating capping layer and the lower surface of the second insulating capping layer have a downwardly concavely rounded profile (Lee in view of Grivna).
Reclaim 16, Lee & Grivna disclose that a first blocking layer covering at least a portion of an the upper surface of the first upper gate electrode, wherein a lower surface of the first blocking layer has a downwardly concavely rounded profile (Lee in view of Grivna).
Reclaim 17, Lee & Grivna disclose that a second blocking layer covering at least a portion of the second upper gate electrode, wherein a vertical level of a lower surface of the second blocking layer is lower than or substantially equal to a vertical level of a the lower surface of the first blocking layer, and the lower surface of the second blocking layer has a downwardly concavely rounded profile (Lee in view of Grivna).
Reclaim 18, Lee & Grivna disclose that the first upper gate electrode and the second upper gate electrode include a material different from a material of the first lower gate electrode and the second lower gate electrode (Lee in view of Grivna).
Reclaim 20, Lee discloses that a first insulating capping layer 251G on the first upper gate electrode;
a second insulating capping layer 251C on the second upper gate electrode;
a first blocking layer 252p located between the first insulating capping layer 251C and the first upper gate electrode; and
a second blocking layer 253p located between the second insulating capping layer and the second upper gate electrode, wherein: a vertical level of a lower surface of the first insulating capping layer is higher than or substantially equal to a vertical level of a lower surface of the second insulating capping layer (Fig. 3K), the lower surface of the first insulating capping layer, the lower surface of the second insulating capping layer, a lower surface of the first blocking layer, and a lower surface of the second blocking layer have a downwardly concavely rounded profile, and a vertical level of the lower surface of the first blocking layer is higher than or substantially equal to a vertical level of the lower surface of the second blocking layer (Lee in view of Grivna’s Fig. 22).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20140291758) in view of Grivna (US 20110136310) and further in view of Jeong (US 20150187899).
Regarding claim 19, Lee & Grivna disclose that an integrated circuit (IC) device, comprising:
a substrate including a first gate trench having a first width in a first horizontal direction and extending in a second horizontal direction orthogonal to the first horizontal direction and a second gate trench apart from the first gate trench in the first horizontal direction, having a depth deeper than a depth of the first gate trench in a vertical direction, and extending in the second horizontal direction;
a gate dielectric layer covering inner surfaces of the first gate trench and the second gate trench;
a first lower gate electrode filling a portion of the first gate trench on the gate dielectric layer;
a second lower gate electrode filling a portion of the second gate trench on the gate dielectric layer;
a first upper gate electrode on the first lower gate electrode in the first gate trench and having a first width in the first horizontal direction; and
a second upper gate electrode on the second lower gate electrode in the second gate trench and having a second width greater than the first width, wherein:
a vertical level of an upper surface and a vertical level of a lower surface of the first upper gate electrode are respectively higher than or substantially equal to a vertical level of an upper surface and a vertical level of a lower surface of the second upper gate electrode, the first upper gate electrode and the second upper gate electrode include doped polysilicon (Lee in view of Grivna) and the second upper gate electrode have an upwardly convexly rounded profile.
Lee & Grivna fail to specify that the first lower gate electrode and the second lower gate electrode include Ti, TiN, Ta, TaN, W, WN, TiSiN, or WSiN, and upper surfaces of the first upper gate electrode.
However, Jeong suggests that lower gate can be Ti, TiN, W, Wn (para. 0032).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Lee with a lower gate electrode can be Ti, TiN, Ta TaN, W, Wn TiSiN. Or WSiN as taught by Jeong in order to enhance material variation and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SU C KIM/ Primary Examiner, Art Unit 2899
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