DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5, 6, & 11-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsieh (US 20090315104).
Regarding claim 1, Hsieh discloses that an integrated circuit (IC) device, comprising:
a substrate having a first gate trench and a second gate trench apart from the first gate trench in a horizontal direction;
a gate dielectric layer 220 covering inner surfaces of the first gate trench and the second gate trench;
a first lower gate line filling a portion of the first gate trench 211 on the gate dielectric layer 220;
a second lower gate line filling a portion of the second gate trench 210 on the gate dielectric layer 220 (Fig. 5 & 6);
a first upper gate line on the first lower gate line in the first gate trench and having a first width in the horizontal direction; and
a second upper gate line on the second lower gate line in the second gate trench and having a second width smaller than the first width, wherein a vertical level of an upper surface of the first upper gate line is higher than or substantially equal to a vertical level of an upper surface of the second upper gate line.
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Reclaim 3, Hsieh discloses that the upper surfaces of the first upper gate line and the second upper gate line are flat (Fig. 6, note: a some portion of the first upper gate line is flat).
Reclaim 5, Hsieh discloses that an uppermost end of a sidewall of the first upper gate line contacting the gate dielectric layer has a vertical level substantially equal to an uppermost surface of the first upper gate line, and an uppermost end of a sidewall of the second upper gate line contacting the gate dielectric layer has a vertical level substantially equal to an uppermost surface of the second upper gate line (Fig. 6).
Reclaim 6, Hsieh discloses that a vertical level of a lower surface of the first upper gate line is substantially equal to a vertical level of a lower surface of the second upper gate line (Fig. 6).
Regarding claim 11, Hsieh discloses that an integrated circuit (IC) device, comprising:
a substrate 200 having a first gate trench and a second gate trench apart from the first gate trench in a horizontal direction (See modified Fig. above);
a gate dielectric layer 220 covering inner surfaces of the first gate trench and the second gate trench (Fig. 5-6);
a first lower gate line 211 filling a portion of the first gate trench on the gate dielectric layer;
a second lower gate line 210 filling a portion of the second gate trench on the gate dielectric layer;
a first upper gate line on the first lower gate line in the first gate trench; and
a second upper gate line on the second lower gate line in the second gate trench, wherein a vertical level of an upper surface of the first upper gate line is higher than or substantially equal to a vertical level of an upper surface of the second upper gate line, and the upper surfaces of the first upper gate line and the second upper gate line have an upwardly convexly rounded profile (Fig. 6 above).
Reclaim 12, Hsieh discloses that a first width of the first gate trench in the horizontal direction is greater than a second width of the second gate trench in the horizontal direction (Fig. 6).
Reclaim 13, Hsieh discloses that an uppermost end of a sidewall of the first upper gate line contacting the gate dielectric layer 220 has a vertical level lower than an uppermost surface of the first upper gate line, and an uppermost end of a sidewall of the second upper gate line contacting the gate dielectric layer has a vertical level lower than an uppermost surface of the second upper gate line (Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 7-10, & 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh (US 20090315104) in view of Tai et al. (US 20110233667 ).
Reclaim 2, Hsieh fails to specify that a depth of the first gate trench in a vertical direction is greater than a depth of the second gate trench in the vertical direction.
However, Tai suggests that a depth of the first gate trench 204 in a vertical direction is greater than a depth of the second gate trench 202 in the vertical direction (Fig. 2B-2).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Hsieh with a depth of the first gate trench in a vertical direction is greater than a depth of the second gate trench in the vertical direction as taught by Tai in order to sufficiently support the breakdown voltage (para. 0027) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 7, Hsieh & Tai disclose that a first insulating capping layer 738 on the first upper gate line in the first gate trench; and
a second insulating capping layer 738 on the second upper gate line in the second gate trench and having a width smaller than a width of the first insulating capping layer (note: Due to size difference), wherein a vertical level of a lower surface of the first insulating capping layer is higher than or substantially equal to a vertical level of a lower surface of the second insulating capping layer (Hsieh in view of Tai’s Fig. 4Q).
Reclaim 8, Hsieh & Tai disclose that the lower surface of the first insulating capping layer and the lower surface of the second insulating capping layer 738 are flat (Hsieh in view of Tai’s Fig. 4Q).
Reclaim 9, Hsieh & Tai disclose that a first blocking layer 738 covering at least a portion of an upper surface of the first upper gate line, wherein a lower surface of the first blocking layer is flat (Hsieh in view of Tai’s Fig. 4Q).
Reclaim 10, Hsieh & Tai disclose that a second blocking layer 738 covering at least a portion of an upper surface of the second upper gate line, wherein a vertical level of the lower surface of the second blocking layer is lower than or substantially equal to a vertical level of the lower surface of the first blocking layer, and the lower surface of the second blocking layer is flat (Hsieh in view of Tai’s Fig. 4Q).
Reclaim 14, Hsieh & Tai disclose that a first insulating capping layer 738 on the first upper gate line; and a second insulating capping layer 738 on the second upper gate line, wherein a vertical level of a lower surface of the first insulating capping layer is higher than or substantially equal to a vertical level of a lower surface of the second insulating capping layer (Hsieh in view of Tai’s Fig. 4Q).
Reclaim 15, Hsieh & Tai disclose that the lower surface of the first insulating capping layer 738 and the lower surface of the second insulating capping layer have a downwardly concavely rounded profile (Hsieh in view of Tai’s Fig. 4Q).
Reclaim 16 Hsieh & Tai disclose that a first blocking layer 738 covering at least a portion of an upper surface of the first upper gate line, wherein a lower surface of the first blocking layer has a downwardly concavely rounded profile (Hsieh in view of Tai’s Fig. 4Q).
Reclaim 17, Hsieh & Tai disclose that a second blocking layer 738 covering at least a portion of the second upper gate line, wherein a vertical level of a lower surface of the second blocking layer is lower than or substantially equal to a vertical level of a lower surface of the first blocking layer, and the lower surface of the second blocking layer has a downwardly concavely rounded profile (Hsieh in view of Tai’s Fig. 4Q).
Reclaim 18, Hsieh & Tai disclose that the first upper gate line and the second upper gate line include a material different from a material of the first lower gate line (note: types of dopant can be varied) and the second lower gate line (Hsieh in view of Tai’s Fig. 4Q, para. Doped po).
Claim(s) 4 & 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh (US 20090315104) in view of Jeong (US 20150187899).
Reclaim 4, Hsieh discloses that the first upper gate line and the second upper gate line include doped polysilicon (para. 0005, Hsieh).
Hsieh fails to teach that the first lower gate line and the second lower gate line include Ti, TiN, Ta, TaN, W, WN, TiSiN, or WSiN.
However, Jeong suggests the first lower gate line and the second lower gate line include Ti, TiN, Ta, TaN, W, WN, TiSiN, or WSiN (para. 0047).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Hsieh with the first lower gate line and the second lower gate line include Ti, TiN, Ta, TaN, W, WN, TiSiN, or WSiN as taught by Jeong in order to enhance variation of gate structures and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Regarding claim 19, Hsieh & Jeong disclose that an integrated circuit (IC) device, comprising:
a substrate 200 including a first gate trench having a first width in a first horizontal direction and extending in a second horizontal direction orthogonal to the first horizontal direction and a second gate trench apart from the first gate trench in the first horizontal direction, having a depth deeper than a depth of the first gate trench in a vertical direction, and extending in the second horizontal direction (Fig. 6);
a gate dielectric layer 210 covering inner surfaces of the first gate trench and the second gate trench (Fig. 6);
a first lower gate line 211’ filling a portion of the first gate trench on the gate dielectric layer (Hsieh, Fig. 6);
a second lower gate line 210 filling a portion of the second gate trench on the gate dielectric layer;
a first upper gate line on the first lower gate line in the first gate trench and having a first width in the horizontal direction (See modified Fig. 6 of Hsieh above); and
a second upper gate line on the second lower gate line in the second gate trench and having a second width greater than the first width (Hsieh, Fig. 6), wherein:
a vertical level of an upper surface and a vertical level of a lower surface of the first upper gate line are respectively higher than or substantially equal to a vertical level of an upper surface and a vertical level of a lower surface of the second upper gate line (See modified Fig. 6 of Hsieh above), the first upper gate line and the second upper gate line include doped polysilicon (para. 0005, Hsieh), the first lower gate line and the second lower gate line include Ti, TiN, Ta, TaN, W, WN, TiSiN, or WSiN (Jeong, para. 0047, Fig. 3), and upper surfaces of the first upper gate line and the second upper gate line have an upwardly convexly rounded profile (Fig. 2, Jeong).
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/SU C KIM/ Primary Examiner, Art Unit 2899