Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 7 and 13
b. Pending: 1-17
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-11, 13-14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Radhakrishnan et al. (US 20110113171) in view of Hwang (US 20120182814).
Regarding independent claim 1, Radhakrishnan discloses a device (Figs. 3-5) comprising:
a clock input port (SCL connected to 116; Fig. 4);
a bidirectional data port (114; Fig. 4 and [0024]);
an address port (118; Fig. 4 and [0025] describes additional serial data input/output (I/O) 118 is selectively configured in the slave device 112 for use in input interrupt mode in a manner to be described so as to assist in detecting receipt of a command);
an address decoder circuit coupled to the clock input port, the bidirectional data port and the address port, the address decoder circuit to receive a clock signal from the clock input port and to receive a data signal from the bidirectional data port, and to decode the clock signal and the data signal to generate a decoded address field and the address decoder circuit to store the value of the address port in a non-transitory storage location and to compare at least one bit of the decoded address field to the stored value of the address port (Figs. 4-5 and [0026] describes slave device 12 first tests in step 200 for reception of a seven bit address in a master-to-slave communication on the serial data line (SDA) which matches the programmed address of that slave device. If a matching address is received in step 200, the slave device 112 configures its additional bi-directional serial data input/output (I/O) 118 in step 202 into input interrupt mode. In this mode, an interrupt signal is generated for each rising edge of the clock signal on the serial clock line (SCL). A test is then made is step 204 as to whether eight interrupts have been counted (one for each of eight consecutive rising clock edges). If not, with each interrupt the process moves to step 206 and the slave device 112 reads the data value present on the serial data line (SDA) at the bi-directional serial data input/output (I/O) 114 for the current clock edge, stores that read value in memory and increments the interrupt counter (i.e., the device executes the associated interrupt servicing program). Thus, the loop formed by steps 204 and 206 functions, after eight iterations and eight interrupt clock edges, to capture and store the subsequent eight bit command code sent by the master 110 to the slave device 112 over the serial data line (SDA) and received by the slave device 112 at the bi-directional serial data input/output (I/O) 114. Here address decoding is inherently done and matching, which means comparison is done), and
Radhakrishnan is silent about an internal control circuit to output a control signal to a pull-down circuit based on a predetermined condition, the pull-down circuit to selectively couple the address port to a ground node based on the value of the control signal.
However, Hwang teaches an internal control circuit to output a control signal to a pull-down circuit based on a predetermined condition, the pull-down circuit to selectively couple the address port to a ground node based on the value of the control signal (Fig. 4 and [0036] describes that first stabilization stage 1000 includes a second buffer IV11 configured to invert, buffer and output the first test address TM_ADD<1>, a first logic element ND10 configured to NAND the output of the second buffer IV11 and the test mode signal TM and output a resultant signal, and a first pull-down element P11 configured to connect the first node nd10 to the ground voltage VSS in response to the output signal of the first logic element ND10 when the first node nd10 is not pull-up driven to the high voltage HV).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Hwang to Radhakrishnan in order to provide programming signal with high reliability as taught by Hwang ([0007]).
Regarding claim 2, Radhakrishnan and Hwang together disclose all the elements of claim 1 as above and through Hwang further the pull-down circuit comprising a metal-oxide semiconductor (MOS) device with a gate node coupled to the control signal, a source node coupled to the ground connection and the drain node coupled to the address port (Fig. 4 and [0036]).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Hwang to modified Radhakrishnan in order to provide programming signal with high reliability as taught by Hwang ([0007]).
Regarding claim 3, Radhakrishnan and Hwang together disclose all the elements of claim 1 as above and through Radhakrishnan further the clock signal comprising an I2C SCL clock signal ([0011] along with Fig. 4 describes I2C SCL clock signal along with I2C bus protocol).
Regarding claim 4, Radhakrishnan and Hwang together disclose all the elements of claim 1 as above and through Radhakrishnan further the data signal comprising an I2C SDA data signal ([0026] along with Fig. 4 describes I2C SDA data signal along with I2C bus protocol).
Regarding claim 5, Radhakrishnan and Hwang together disclose all the elements of claim 1 as above and through Radhakrishnan further the predetermined condition comprising a system alert (Figs. 4-5 and [0027] describes signal indicating an acknowledgement (ACK) of receipt in step 212, which is comparable to alert signal of Fig. 3).
Regarding independent claim 7, Radhakrishnan discloses a system (Figs. 3-5) comprising:
a primary device to drive a clock bus (Fig. 3 shows clock bus SCL) and a data bus (Fig. 3 shows data bus SDA) and to couple to a control bus (Fig. 3 shows control signal line ALERT); a plurality of secondary devices (Fig. 3 shows multiple slave devices) comprising:
a clock input port to couple to the clock bus (Fig. 4 and [0024] describes clock input (CLK) 116 connected to the serial clock line (SCL));
a bidirectional data port to couple to the data bus (Fig. 4 and [0024] describes bi-directional serial data input/output (DATA) 114 connected to the serial data line (SDA));
an address port to couple to the control bus (118; Fig. 4 and [0025] describes additional serial data input/output (I/O) 118 is selectively configured in the slave device 112 for use in input interrupt mode in a manner to be described so as to assist in detecting receipt of a command);
an address decoder circuit coupled to the clock input port, the bidirectional data port and the address port, the address decoder circuit to receive a clock signal from the clock input port and to receive a data signal from the bidirectional data port, and to decode the clock signal and the data signal to generate a decoded address field and the address decoder circuit to store the value of the address port in a non-transitory storage location and to compare at least one bit of the decoded address field to the stored value of the address port (Figs. 4-5 and [0026] describes slave device 12 first tests in step 200 for reception of a seven bit address in a master-to-slave communication on the serial data line (SDA) which matches the programmed address of that slave device. If a matching address is received in step 200, the slave device 112 configures its additional bi-directional serial data input/output (I/O) 118 in step 202 into input interrupt mode. In this mode, an interrupt signal is generated for each rising edge of the clock signal on the serial clock line (SCL). A test is then made is step 204 as to whether eight interrupts have been counted (one for each of eight consecutive rising clock edges). If not, with each interrupt the process moves to step 206 and the slave device 112 reads the data value present on the serial data line (SDA) at the bi-directional serial data input/output (I/O) 114 for the current clock edge, stores that read value in memory and increments the interrupt counter (i.e., the device executes the associated interrupt servicing program). Thus, the loop formed by steps 204 and 206 functions, after eight iterations and eight interrupt clock edges, to capture and store the subsequent eight bit command code sent by the master 110 to the slave device 112 over the serial data line (SDA) and received by the slave device 112 at the bi-directional serial data input/output (I/O) 114. Here address decoding is inherently done and matching, which means comparison is done), and
Radhakrishnan is silent about an internal control circuit to output a control signal to a pull-down circuit based on a predetermined condition, the pull-down circuit to selectively couple the address port to a ground node based on the value of the control signal.
However, Hwang teaches an internal control circuit to output a control signal to a pull-down circuit based on a predetermined condition, the pull-down circuit to selectively couple the address port to a ground node based on the value of the control signal (Fig. 4 and [0036] describes that first stabilization stage 1000 includes a second buffer IV11 configured to invert, buffer and output the first test address TM_ADD<1>, a first logic element ND10 configured to NAND the output of the second buffer IV11 and the test mode signal TM and output a resultant signal, and a first pull-down element P11 configured to connect the first node nd10 to the ground voltage VSS in response to the output signal of the first logic element ND10 when the first node nd10 is not pull-up driven to the high voltage HV).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Hwang to Radhakrishnan in order to provide programming signal with high reliability as taught by Hwang ([0007]).
Regarding claim 8, Radhakrishnan and Hwang together disclose all the elements of claim 7 as above and through Hwang further the pull-down circuit comprising a metal-oxide semiconductor (MOS) device with a gate node coupled to the control signal, a source node coupled to the ground connection and the drain node coupled to the address port (Fig. 4 and [0036]).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Hwang to modified Radhakrishnan in order to provide programming signal with high reliability as taught by Hwang ([0007]).
Regarding claim 9, Radhakrishnan and Hwang together disclose all the elements of claim 7 as above and through Radhakrishnan further the clock signal comprising an I2C SCL clock signal ([0011] along with Fig. 4 describes I2C SCL clock signal along with I2C bus protocol).
Regarding claim 10, Radhakrishnan and Hwang together disclose all the elements of claim 7 as above and through Radhakrishnan further the data signal comprising an I2C SDA data signal ([0026] along with Fig. 4 describes I2C SDA data signal along with I2C bus protocol).
Regarding claim 11, Radhakrishnan and Hwang together disclose all the elements of claim 7 as above and through Radhakrishnan further the predetermined condition comprising a system alert (Figs. 4-5 and [0027] describes signal indicating an acknowledgement (ACK) of receipt in step 212, which is comparable to alert signal of Fig. 3).
Regarding independent claim 13, Radhakrishnan discloses a method (Figs. 3-5) comprising:
receiving a data transmission from a primary device at a secondary device (Figs. 3-4 shows master device and slave device),
storing the value of an address port to a stored address location in a non-transitory storage device, decoding the data transmission to generate a decoded address field, comparing at least one bit of the decoded address field with the stored address port value (Figs. 4-5 and [0026] describes slave device 12 first tests in step 200 for reception of a seven bit address in a master-to-slave communication on the serial data line (SDA) which matches the programmed address of that slave device. If a matching address is received in step 200, the slave device 112 configures its additional bi-directional serial data input/output (I/O) 118 in step 202 into input interrupt mode. In this mode, an interrupt signal is generated for each rising edge of the clock signal on the serial clock line (SCL). A test is then made is step 204 as to whether eight interrupts have been counted (one for each of eight consecutive rising clock edges). If not, with each interrupt the process moves to step 206 and the slave device 112 reads the data value present on the serial data line (SDA) at the bi-directional serial data input/output (I/O) 114 for the current clock edge, stores that read value in memory and increments the interrupt counter (i.e., the device executes the associated interrupt servicing program). Thus, the loop formed by steps 204 and 206 functions, after eight iterations and eight interrupt clock edges, to capture and store the subsequent eight bit command code sent by the master 110 to the slave device 112 over the serial data line (SDA) and received by the slave device 112 at the bi-directional serial data input/output (I/O) 114. Here address decoding is inherently done and matching, which means comparison is done), and
Radhakrishnan is silent about pulling down the voltage of the address port, based on a predetermined condition of the secondary device, to signal a status condition to the primary device.
However, Hwang teaches pulling down the voltage of the address port, based on a predetermined condition of the secondary device, to signal a status condition to the primary device (Fig. 4 and [0036] describes that first stabilization stage 1000 includes a second buffer IV11 configured to invert, buffer and output the first test address TM_ADD<1>, a first logic element ND10 configured to NAND the output of the second buffer IV11 and the test mode signal TM and output a resultant signal, and a first pull-down element P11 configured to connect the first node nd10 to the ground voltage VSS in response to the output signal of the first logic element ND10 when the first node nd10 is not pull-up driven to the high voltage HV).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Hwang to Radhakrishnan in order to provide programming signal with high reliability as taught by Hwang ([0007]).
Regarding claim 14, Radhakrishnan and Hwang together disclose all the elements of claim 13 as above and through Radhakrishnan further the predetermined condition comprising a system alert (Figs. 4-5 and [0027] describes signal indicating an acknowledgement (ACK) of receipt in step 212, which is comparable to alert signal of Fig. 3).
Regarding claim 16, Radhakrishnan and Hwang together disclose all the elements of claim 13 as above and through Radhakrishnan further the data transmission comprising an I2C write transmission ([0010] describes write transmission).
Regarding claim 17, Radhakrishnan and Hwang together disclose all the elements of claim 13 as above and through Radhakrishnan further the data transmission comprising an I2C read transmission ([0010] describes write transmission).
Claims 6, 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Radhakrishnan et al. (US 20110113171) in view of Hwang (US 20120182814) and Gopalraju et al. (CN 106030435).
Regarding claim 6, Radhakrishnan and Hwang together disclose all the elements of claim 1 as above and through Gopalraju further the predetermined condition comprising a thermal limit (Claim 21 recites a pull-down circuit for in response to the output voltage rises to more than the second reference voltage substantially constant amount of current being drawn from the circuit, and in response to the output voltage drops below the second reference voltage at a predetermined amount so as to stop drawing the current from the circuit. wherein the second reference voltage is equal to the target voltage delta LOV-state, wherein delta LOV-state is the level for detecting a predetermined condition, and, wherein the second reference voltage is lower than the maximum allowed by the output voltage level, wherein the first and second reference voltages are based on the same band gap reference, the regulator and the pull-down circuit are equally affected by changing of one or more environmental condition and the environment condition comprises at least one of process, voltage and temperature).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Gopalraju to modified Radhakrishnan in order to provide advantage over conventional state machine technology which has long: (a) stable time of the one or more ambient condition, and increased (b) overshoot state occurrence probability of undershoot state as taught by Gopalraju (Fig. 3 and corresponding sections of the Specification).
Regarding claim 12, Radhakrishnan and Hwang together disclose all the elements of claim 7 as above and through Gopalraju further the predetermined condition comprising a thermal limit (Claim 21 recites a pull-down circuit for in response to the output voltage rises to more than the second reference voltage substantially constant amount of current being drawn from the circuit, and in response to the output voltage drops below the second reference voltage at a predetermined amount so as to stop drawing the current from the circuit. wherein the second reference voltage is equal to the target voltage delta LOV-state, wherein delta LOV-state is the level for detecting a predetermined condition, and, wherein the second reference voltage is lower than the maximum allowed by the output voltage level, wherein the first and second reference voltages are based on the same band gap reference, the regulator and the pull-down circuit are equally affected by changing of one or more environmental condition and the environment condition comprises at least one of process, voltage and temperature).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Gopalraju to modified Radhakrishnan in order to provide advantage over conventional state machine technology which has long: (a) stable time of the one or more ambient condition, and increased (b) overshoot state occurrence probability of undershoot state as taught by Gopalraju (Fig. 3 and corresponding sections of the Specification).
Regarding claim 15, Radhakrishnan and Hwang together disclose all the elements of claim 13 as above and through Gopalraju further the predetermined condition comprising a thermal limit (Claim 21 recites a pull-down circuit for in response to the output voltage rises to more than the second reference voltage substantially constant amount of current being drawn from the circuit, and in response to the output voltage drops below the second reference voltage at a predetermined amount so as to stop drawing the current from the circuit. wherein the second reference voltage is equal to the target voltage delta LOV-state, wherein delta LOV-state is the level for detecting a predetermined condition, and, wherein the second reference voltage is lower than the maximum allowed by the output voltage level, wherein the first and second reference voltages are based on the same band gap reference, the regulator and the pull-down circuit are equally affected by changing of one or more environmental condition and the environment condition comprises at least one of process, voltage and temperature).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Gopalraju to modified Radhakrishnan in order to provide advantage over conventional state machine technology which has long: (a) stable time of the one or more ambient condition, and increased (b) overshoot state occurrence probability of undershoot state as taught by Gopalraju (Fig. 3 and corresponding sections of the Specification).
Response to Arguments
Applicant's arguments filed 8/5/2025 have been fully considered but examiner respectfully disagrees.
In response to applicant's argument “the prior art invention being modified unsatisfactory”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Examiner suggests that the features upon which applicant relies need to be recited in the claim(s).
Rejections are maintained for above reasons.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 2/11/2026