DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-6 in the reply filed on 02/20/2026 is acknowledged.
Claims 7-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/20/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0115384 to An et al. (hereinafter An) in view of Wu (US 2015/0001602).
With respect to claim 1, An discloses a semiconductor memory device (e.g., Dynamic Random Access Memory (DRAM), see the annotated Figs. 1, 22, and 23 below) (An, Figs.1-2, 22-23, ¶0002-¶0003, ¶0018-¶0121), comprising:
a substrate (310) (An, Figs.1-2, 22-23, ¶0018-¶0020, ¶0024, ¶0107) including a cell array area (CELL) and a core area (CORE/PERI) near the cell array area, the cell array area including a direct contact hole (TR) (An, Figs. 15, 22-23, ¶0019, ¶0077, ¶0080, ¶0106) exposing an active region (AR) (An, Figs. 22-23, ¶0024, ¶0107, ¶0109);
a buried contact (BC) (An, Figs. 22-23, ¶0019, ¶0102-¶0104, ¶0106) in the cell array area (CELL), the buried contact (BC) being connected to a storage element (790) (An, Figs. 22-23, ¶0019, ¶0114-¶0119);
a direct contact (DC) (An, Figs. 22-23, ¶0019, ¶0080, ¶0084, ¶0106) in the cell array area (CELL), the direct contact including an upper layer (e.g., above the substrate 310) and a lower layer (e.g., below the substrate 310), and the lower layer being in the direct contact hole in direct contact with the active region (AR);
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bit lines (BL, 740/760) (An, Figs. 22-23, ¶0019, ¶0106, ¶0108-¶0109) in contact with the upper layer of the direct contact (DC).
Further, An does not specifically disclose that the upper layer including a metal, and the lower layer including a silicide of the metal; and word lines crossing the bit lines.
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However, Wu teaches forming a Dynamic Random Access Memory (DRAM, see the annotated Fig. 4 below) (Wu, Figs. 1-5, ¶0002-¶0003, ¶0031-¶0033, ¶0078-¶0209) that includes a memory cell section (11) (Wu, Figs. 1-5, ¶0078-¶0098) which contains word lines (e.g., embedded gate electrodes 83/91) (Wu, Figs. 1-5, ¶0103-¶0104, ¶0111, ¶0121-¶0122) and bit lines (33) (Wu, Figs. 1-5, ¶0078, ¶0130- ¶0139), and a peripheral circuit section (12) (Wu, Fig. 1, ¶0083) which is arranged around the memory cell section (11) and drives memory cells of the memory cell section, wherein the word lines are embedded in a semiconductor substrate and the bit lines are formed on the semiconductor substrate, to provide miniaturization of the DRAM memory cells.
The bit lines (33) (Wu, Figs. 1-5, ¶0078, ¶0130- ¶0139) include bit contacts (101/102) in the bit contact holes (28A) that expose an upper surface (17a/87a) of the cell active regions (17/87), wherein the bit contacts (101/102) include the upper layer (102) including a metal (e.g., Ti) (Wu, Figs. 3-4, ¶0139), and the lower layer (101) being in the direct contact hole (28A) in direct contact with the active region (17/87) and including a silicide of the metal (e.g., titanium silicide) (Wu, Figs. 3-4, ¶0137), to lower contact resistance between the bit line and the active region (Wu, ¶0138).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of An by forming a memory cell including the word lines are embedded in a semiconductor substrate and the bit lines are formed on the semiconductor substrate as taught by Wu, wherein the bit line contact includes a lower layer made of silicide material as taught by Wu to have the semiconductor memory device, wherein the upper layer including a metal, and the lower layer including a silicide of the metal; and word lines crossing the bit lines, in order to provide miniaturization of the DRAM memory cells, and to lower contact resistance between the bit line and the active region, and thus to improve accuracy of the operation of DRAM (Wu, ¶0031, ¶0033, ¶0035, ¶0138).
Regarding claims 2 and 3, An in view of Wu discloses the semiconductor memory device as claimed in claim 1. Further, An does not specifically disclose that the upper layer includes at least one of W, Rh, Cu, Co, Mo, and TiN (as claimed in claim 2); wherein the upper layer includes TiN (as claimed in claim 3).
However, Wu teaches forming the bit lines (33) (Wu, Figs. 1-5, ¶0078, ¶0130- ¶0139) including bit contacts (101/102) in the bit contact holes (28A), wherein the bit contacts (101/102) include the upper layer (102) including a metal (e.g., titanium nitride) (Wu, Figs. 3-4, ¶0139), and the lower layer (101) including a silicide of the metal (e.g., titanium silicide) (Wu, Figs. 3-4, ¶0137), to lower contact resistance between the bit line and the active region (Wu, ¶0138).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of An/Wu by forming the bit lines including a lower layer made of titanium silicide and an upper layer including titanium nitride as taught by Wu to have the semiconductor memory device, wherein the upper layer includes TiN as claimed in claim 2); wherein the upper layer includes TiN (as claimed in claim 3), in order to lower contact resistance between the bit line and the active region, and thus to improve accuracy of the operation of DRAM (Wu, ¶0031, ¶0033, ¶0035, ¶0138).
Regarding claim 4, An in view of Wu discloses the semiconductor memory device as claimed in claim 1. Further, An discloses the semiconductor memory device, further comprising a cell insulating film (e.g., the base insulating film 730) (An, Fig. 23, ¶0019, ¶0098-¶0099, ¶0106) on the substrate (310), the cell insulating film (730) not overlapping the buried contact (BC) and the direct contact (DC).
Regarding claim 5, An in view of Wu discloses the semiconductor memory device as claimed in claim 4. Further, An discloses the semiconductor memory device, wherein the cell insulating film (e.g., the base insulating film 730 is similar to the base insulating film 330) has a three-layer structure (731/732/733) (An, Fig. 23, ¶0032, ¶0038, ¶0098-¶0099, ¶0106).
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139927 to Chang et al. (hereinafter Chang) in view of Wu (US 2015/0001602).
With respect to claim 1, Chang discloses a semiconductor memory device (e.g., Dynamic Random Access Memory (DRAM), see the annotated Figs. 1-2 and 4 below) (Chang, Figs. 1-8, ¶0002-¶0003, ¶0027-¶0128), comprising:
a substrate (100) (Chang, Figs. 1-8, ¶0030-¶0032, ¶0043) including a cell array area (20) and a core area (e.g., peripheral region 24) near the cell array area (20), the cell array area (20) including a direct contact hole (e.g., bit contact hole for a direct contact DC) (Chang, Figs.1-8, ¶0036, ¶0058-¶0059) exposing an active region (ACT) (Chang, Figs. 1-8, ¶0032-¶0034, ¶0037, ¶0045);
a buried contact (BC, 120) (Chang, Figs. 1, 4, ¶0036, ¶0074) in the cell array area (20), the buried contact (BC) being connected to a storage element (190) (Chang, Figs. 1, 4, ¶0037, ¶0082);
a direct contact (DC, 146) (Chang, Figs. 1, 4, ¶0036, ¶0039, ¶0058-¶0059) in the cell array area (20), the direct contact (DC) including an upper layer (e.g., above the substrate 100) and a lower layer (e.g., below the substrate 100), and the lower layer being in the direct contact hole in direct contact with the active region (ACT);
bit lines (BL, 140) (Chang, Figs. 1, 4, ¶0035, ¶0055-¶0056) in contact with the upper layer of the direct contact (DC); and
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word lines (WL, 112) (Chang, Figs. 1, 5, ¶0035, ¶0049-¶0052) crossing the bit lines (BL).
Further, Chang does not specifically disclose that the upper layer including a metal, and the lower layer including a silicide of the metal.
However, Wu teaches forming a Dynamic Random Access Memory (DRAM, see the annotated Fig. 4 above) (Wu, Figs. 1-5, ¶0002-¶0003, ¶0031-¶0033, ¶0078-¶0209) that includes a memory cell section (11) (Wu, Figs. 1-5, ¶0078-¶0098) which contains word lines (e.g., embedded gate electrodes 83/91) (Wu, Figs. 1-5, ¶0103-¶0104, ¶0111, ¶0121-¶0122) and bit lines (33) (Wu, Figs. 1-5, ¶0078, ¶0130- ¶0139), and a peripheral circuit section (12) (Wu, Fig. 1, ¶0083) which is arranged around the memory cell section (11) and drives memory cells of the memory cell section, wherein the word lines are embedded in a semiconductor substrate and the bit lines are formed on the semiconductor substrate, to provide miniaturization of the DRAM memory cells. The bit lines (33) (Wu, Figs. 1-5, ¶0078, ¶0130- ¶0139) include bit contacts (101/102) in the bit contact holes (28A) that expose an upper surface (17a/87a) of the cell active regions (17/87), wherein the bit contacts (101/102) include the upper layer (102) including a metal (e.g., Ti) (Wu, Figs. 3-4, ¶0139), and the lower layer (101) being in the direct contact hole (28A) in direct contact with the active region (17/87) and including a silicide of the metal (e.g., titanium silicide) (Wu, Figs. 3-4, ¶0137), to lower contact resistance between the bit line and the active region (Wu, ¶0138).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Chang by forming the bit lines on the semiconductor substrate as taught by Wu, wherein the bit line contact includes a lower layer made of a silicide material as taught by Wu to have the semiconductor memory device, wherein the upper layer including a metal, and the lower layer including a silicide of the metal, in order to provide miniaturization of the DRAM memory cells, and to lower contact resistance between the bit line and the active region, and thus to improve accuracy of the operation of DRAM (Wu, ¶0031, ¶0033, ¶0035, ¶0138).
Regarding claims 2 and 3, Chang in view of Wu discloses the semiconductor memory device as claimed in claim 1. Further, Chang does not specifically disclose that the upper layer includes at least one of W, Rh, Cu, Co, Mo, and TiN (as claimed in claim 2); wherein the upper layer includes TiN (as claimed in claim 3).
However, Wu teaches forming the bit lines (33) (Wu, Figs. 1-5, ¶0078, ¶0130- ¶0139) including bit contacts (101/102) in the bit contact holes (28A), wherein the bit contacts (101/102) include the upper layer (102) including a metal (e.g., titanium nitride) (Wu, Figs. 3-4, ¶0139), and the lower layer (101) including a silicide of the metal (e.g., titanium silicide) (Wu, Figs. 3-4, ¶0137), to lower contact resistance between the bit line and the active region (Wu, ¶0138).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Chang/Wu by forming the bit lines including a lower layer made of titanium silicide and an upper layer including titanium nitride as taught by Wu to have the semiconductor memory device, wherein the upper layer includes TiN as claimed in claim 2); wherein the upper layer includes TiN (as claimed in claim 3), in order to lower contact resistance between the bit line and the active region, and thus to improve accuracy of the operation of DRAM (Wu, ¶0031, ¶0033, ¶0035, ¶0138).
Regarding claim 4, Chang in view of Wu discloses the semiconductor memory device as claimed in claim 1. Further, Chang discloses the semiconductor memory device, further comprising a cell insulating film (e.g., the base insulating film 130) (Chang, Fig. 4, ¶0062-¶0063) on the substrate (100), the cell insulating film (130) not overlapping the buried contact (BC) and the direct contact (DC).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139927 to Chang in view of Wu (US 2015/0001602) as applied to claim 4, and further in view of An (2022/0115384) and Kim et al. (US 2023/0328960, hereinafter Kim).
Regarding claims 5 and 6, Chang in view of Wu discloses the semiconductor memory device as claimed in claim 4. Further, Chang discloses the semiconductor memory device, wherein the cell insulating film (130) (Chang, Fig. 4, ¶0062-¶0063) has a two-layer structure, wherein: the cell insulating film (130) includes a first insulating film (131), a second insulating film (132) that are sequentially stacked, the first insulating film (131) includes a semiconductor oxide film (e.g., silicon oxide), but does not specifically disclose a three-layer structure (as claimed in claim 5); a third insulating film, the second insulating film includes a metal oxide film, and the third insulating film includes a semiconductor nitride film (as claimed in claim 6).
However, An teaches forming a cell insulating film (e.g., the base insulating film 730 is similar to the base insulating film 330) having a three-layer structure (731/732/733) (An, Fig. 23, ¶0032, ¶0038, ¶0098-¶0099, ¶0106), wherein a first insulating film (731/331), a second insulating film (732/332), and a third insulating film (733/333) that are sequentially stacked, the first insulating film (731/331) includes a semiconductor oxide film (e.g., silicon oxide), and a material of the second insulating film (732/332) (An, Fig. 23, ¶0038) has etching selectivity different from that of the first insulating film (731/331), to provide improved highly integrated DRAM memory with reduced current leakage and parasitic capacitance (An, Fig. 23, ¶0002, ¶0123).
Further, Kim teaches forming a cell surface insulating layer (21) (Kim, Fig. 1A-1B, ¶0004, ¶0024, ¶0026, ¶0058, ¶0063-¶0064) over the substrate (10) in the cell area (CA) and including at least one of a silicon oxide layer, silicon nitride layer, and a metal oxide layer, to provide improved DRAM memory having buried channel array.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Chang/Wu by forming a cell surface insulating layer including a plurality of insulating layers having different etching selectivity as taught by An, wherein the plurality of insulating layers includes silicon oxide, metal oxide, and silicon nitride as taught by Kim to have the semiconductor memory device, wherein the cell insulating film has a three-layer structure (as claimed in claim 5); wherein: the cell insulating film includes a third insulating film, the second insulating film includes a metal oxide film, and the third insulating film includes a semiconductor nitride film (as claimed in claim 6), in order to provide improved highly integrated DRAM memory having buried channel array, and with reduced current leakage and parasitic capacitance (An, ¶0002, ¶0123; Kim, ¶0004, ¶0026, ¶0058, ¶0063-¶0064).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0115384 to An in view of Wu (US 2015/0001602) as applied to claim 5, and further in view of Kim (US 2023/0328960).
Regarding claim 6, An in view of Wu discloses the semiconductor memory device as claimed in claim 5. Further, An discloses the semiconductor memory device, wherein the cell insulating film (e.g., the base insulating film 730 formed as the base insulating film 330) (An, Fig. 23, ¶0019, ¶0038, ¶0098-¶0099, ¶0106) includes a first insulating film (731/331), a second insulating film (732/332), and a third insulating film (733/333) that are sequentially stacked, the first insulating film (731/331) includes a semiconductor oxide film (e.g., silicon oxide), but does not specifically disclose the second insulating film includes a metal oxide film, and the third insulating film includes a semiconductor nitride film.
However, An teaches that a material of the second insulating film (732/332) (An, Fig. 23, ¶0038) has etching selectivity different from that of the first insulating film (731/331), to provide improved highly integrated DRAM memory with reduced current leakage and parasitic capacitance (An, Fig. 23, ¶0002, ¶0123).
Further, Kim teaches forming a cell surface insulating layer (21) (Kim, Fig. 1A-1B, ¶0004, ¶0024, ¶0026, ¶0058, ¶0063-¶0064) over the substrate (10) in the cell area (CA) and including at least one of a silicon oxide layer, silicon nitride layer, and a metal oxide layer, to provide improved DRAM memory having buried channel array.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of An/Wu by forming a cell surface insulating layer including a plurality of insulating layers having different etching selectivity as taught by An, wherein the plurality of insulating layers includes silicon oxide, metal oxide, and silicon nitride as taught by Kim to have the semiconductor memory device, wherein the second insulating film includes a metal oxide film, and the third insulating film includes a semiconductor nitride film, in order to provide improved highly integrated DRAM memory having buried channel array, and with reduced current leakage and parasitic capacitance (An, ¶0002, ¶0123; Kim, ¶0004, ¶0026, ¶0058, ¶0063-¶0064).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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