DETAILED ACTION
This action is in response to an amendment filed 2/6/26.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the first vertical arrangement of semiconductor nanowires having a greater number of nanowires than the second vertical arrangement of semiconductor nanowires” and “the first vertical arrangement of semiconductor nanowires having a bottommost semiconductor nanowire below a semiconductor bottommost nanowire of the second arrangement of nanowires” in combination with “the first and second vertical arrangements of semiconductor nanowires having uppermost semiconductor nanowires in a same horizontal plane” (from at least claims 1 and 14) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 3-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 14 state “the first vertical arrangement of semiconductor nanowires having a bottommost semiconductor nanowire below a bottommost semiconductor nanowire of the second arrangement of semiconductor nanowires”. The subject matter of claims 1 and 14 generally appears to coincide with the Fig. 7(e) of the Drawings its associated text from the Specification since only Fig. 7 illustrates at least two vertical arrangements of nanowires having uppermost semiconductor nanowires “at a same level”. However, paragraph [0107] of the Specification discloses “The first and second vertical arrangements of nanowires have co-planar uppermost nanowires and co-planar bottommost nanowires.” Therefore, it is unclear how the first vertical arrangement of semiconductor nanowires has a bottommost nanowire below a bottommost nanowire of the second arrangement of semiconductor nanowires when the Specification states when the first and second vertical arrangements of nanowires have co-planar uppermost semiconductor nanowires, they also have co-planar bottommost nanowires. Said another way, if the bottommost nanowires are co-planar according to paragraph [0107], how can the first vertical arrangement of semiconductor nanowires have a bottommost semiconductor nanowire below a bottommost nanowire of the second arrangement of nanowires, as required by claims 1 and 14?
Claims 3-13 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 1. Claims 15-20 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 14.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 11, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Lee et al. (U.S. 2017/0140933 A1; “Lee”) in view of Hung et al. (U.S. 2023/0065195 A1; “Hung”).
Regarding claim 1, Lee discloses an integrated circuit structure, comprising:
A first vertical arrangement of semiconductor nanowires (123, Fig. 1J) and a second vertical arrangement of semiconductor nanowires (125, Fig. 1J) above a substrate (102, Fig. 1J), the first vertical arrangement of semiconductor nanowires (123, Fig. 1J) having a greater number of semiconductor nanowires than the second vertical arrangement of semiconductor nanowires (125, Fig. 1J), the first (123, Fig. 1J) and second (125, Fig. 1J) vertical arrangements of semiconductor nanowires having uppermost semiconductor nanowires in a same horizontal plane, and the first vertical arrangement of semiconductor nanowires (123, Fig. 1J) having a bottommost semiconductor nanowire below a bottommost semiconductor nanowire of the second arrangement of semiconductor nanowires (125, Fig. 1J) ([0021]);
An oxide structure (“interfacial layer”) vertically beneath the bottommost semiconductor nanowire of the second arrangement of semiconductor nanowires (125, Fig. 1J), wherein the bottommost semiconductor nanowire of the second arrangement of semiconductor nanowires is vertically overlapping with the oxide structure along a vertical axis ([0035]: “like the gate structure 124, gate structure 128 may include an interfacial layer, a high-k dielectric layer, and a metal gate layer” in conjunction with [0019]: “interfacial layer may wrap around and contact each side of the elongated semiconductor materials” and “the interfacial layer may include an oxide-containing material….”) and the oxide structure (“interfacial layer”) is in a same horizontal plane as the bottommost semiconductor nanowire of the first vertical arrangement of semiconductor nanowires (since the bottommost semiconductor nanowire of the second vertical arrangement of semiconductor nanowires 125 at least partially laterally overlaps the bottommost semiconductor of the first vertical arrangement of semiconductors 123, an interfacial layer contacting each side of the bottommost semiconductor nanowire of the second vertical arrangement of semiconductor nanowires 125 would necessarily be partially in at least a same horizontal plane as a portion of the bottommost semiconductor of the first vertical arrangement of semiconductors 123);
A first gate stack (124, Fig. 1J) over the first vertical arrangement of semiconductor nanowires (123, Fig. 1J) ([0027]); and
A second gate stack (128, Fig. 1J) over the second vertical arrangement of semiconductor nanowires (125, Fig. 1J) and over the oxide structure ([0034]-[0035], [0019]; though not illustrated, the interfacial layer of the second gate stack is formed like the first gate stack ([0035]), wherein the interfacial layer is formed first and wraps arounds and contacts each side of the elongated semiconductor materials ([0019]) and wherein the metal gate layer wraps around each side of the elongated semiconductor features ([0034]). If the metal gate layer [of the second gate stack] wraps around each side of the elongated semiconductor features, wherein the interfacial layer wraps around and contacts each side of the elongated semiconductor features but is formed first, then the metal gate layer would necessarily wrap around and be over and contact each side of the interfacial layer).
Alternatively, assuming arguendo that the description in Lee does not implicitly illustrate the oxide structure (“interfacial layer”) vertically beneath the bottommost semiconductor nanowire of the second arrangement of semiconductor nanowires wherein the bottom nanowire of the second arrangement of semiconductor nanowires is vertically overlapping with the oxide structure along a vertical axis, and the oxide structure is in a same horizontal plane as the bottommost semiconductor nanowire of the first vertical arrangement of semiconductor nanowires, Hung discloses an oxide structure (260, Fig. 25) vertically beneath (portion of 260 under 216, Fig. 25) the bottommost semiconductor nanowire (bottommost 216, Fig. 25) of an arrangement of semiconductor nanowires. Hung further discloses a gate stack (290, Fig. 25) over the vertical arrangement of semiconductor nanowires (216, Fig. 25) and over the oxide structure (260, Fig. 25). This has the advantage of enhanced gate control and reduced leakage current.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lee with the oxide structure such that the second gate stack is over and around the second vertical arrangement of semiconductor nanowires and over and around the oxide structure, as taught by Hung, so as to enhance gate control and reduce leakage current.
As to the limitation the oxide structure (“interfacial layer”) is in a same horizontal plane as the bottommost semiconductor nanowire of the first vertical arrangement of semiconductor nanowires, since according to Lee the bottommost semiconductor nanowire of the second vertical arrangement of semiconductor nanowires (Lee: 125, Fig. 1J) at least partially laterally overlaps the bottommost semiconductor of the first vertical arrangement of semiconductors (Lee: 123, Fig. 1J), an interfacial layer, as taught by Hung, contacting each side of the bottommost semiconductor nanowire of the second vertical arrangement of semiconductor nanowires would necessarily be partially in at least a same horizontal plane as a portion of the bottommost semiconductor of the first vertical arrangement of semiconductors.
Regarding claim 11, Lee discloses the first vertical arrangement of semiconductor nanowires (123, Fig. 1J) is over a first fin (vertically protruding portion of 102 under 223, Fig. 1J), and the second vertical arrangement of semiconductor nanowires (125, Fig. 1J) is over a second fin (vertically protruding portion of 102 under 225, Fig. 1J).
Regarding claim 13, Lee discloses the first (124, Fig. 1J) and second (128, Fig. 1J) gate stacks each comprise a high-k gate dielectric layer and a metal gate electrode ([0029], [0035]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2017/0140933 A1; “Lee”) or Lee (U.S. 2017/0140933 A1; “Lee”) in view of Hung et al. (U.S. 2023/0065195 A1; “Hung”) as applied to claim 1 above, and further in view of Chang et al. (U.S. 2014/0151638 A1; “Chang”).
Regarding claim 3, Lee discloses the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires (123, Fig. 1J) have a horizontal width and the nanowires of the second vertical arrangement of semiconductor nanowires (125, Fig. 1J) have a horizontal width ([0026], [0033]). Yet, Lee does not explicitly disclose the horizontal width of the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires is same as the horizontal width of the nanowires of the second vertical arrangement of semiconductor nanowires. However, Chang discloses a horizontal width of semiconductor nanowires of a first vertical arrangement of nanowires is the same as the horizontal width of the semiconductor nanowires of a second vertical arrangement of semiconductor nanowires ([0081]). This has the advantage of increasing uniformity of the overall device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lee or Lee in view of Hung with a horizontal width of semiconductor nanowires of a first vertical arrangement of semiconductor nanowires is the same as the horizontal width of the semiconductor nanowires of a second vertical arrangement of semiconductor nanowires, as taught by Chang, so as to increase uniformity of the overall device.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2017/0140933 A1; “Lee”) or Lee (U.S. 2017/0140933 A1; “Lee”) in view of Hung et al. (U.S. 2023/0065195 A1; “Hung”) as applied to claim 1 above.
Regarding claims 4, Lee discloses the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires (123, Fig. 1J) have a horizontal width and the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires (125, Fig. 1J) have a horizontal width ([0026], [0033]). Lee further discloses the horizontal widths of the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires and the horizontals widths of the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires may differ from each other ([0026], [0033]). Yet, Lee does not explicitly disclose the horizontal width of the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires is greater than the horizontal width of the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires.
However, one of ordinary skill in the art would have recognized the finite number of predictable solutions to differ the horizontal widths between the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires and the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires: either the horizontal width of the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires is greater than the horizontal width of the nanowires of the second vertical arrangement of semiconductor nanowires; or, the horizontal width of the semiconductor nanowires of the first vertical arrangement of nanowires is less than the horizontal width of the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires. Thus, it would have been obvious to select dimensions such that the horizontal width of the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires is greater than the horizontal width of the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires since it has been held that it is obvious to try from a finite number of identified, predictable solutions with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 5, Lee discloses the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires (123, Fig. 1J) have a horizontal width and the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires (125, Fig. 1J) have a horizontal width ([0026], [0033]). Lee further discloses the horizontal widths of the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires and the semiconductor horizontals widths of the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires may differ from each other ([0026], [0033]). Yet, Lee does not explicitly disclose the horizontal width of the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires is less than the horizontal width of the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires.
However, one of ordinary skill in the art would have recognized the finite number of predictable solutions to differ the horizontal widths between the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires and the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires: either the horizontal width of the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires is greater than the horizontal width of the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires; or, the horizontal width of the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires is less than the horizontal width of the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires. Thus, it would have been obvious to select dimensions such that the horizontal width of the semiconductor nanowires of the first vertical arrangement of semiconductor nanowires is less than the horizontal width of the semiconductor nanowires of the second vertical arrangement of semiconductor nanowires since it has been held that it is obvious to try from a finite number of identified, predictable solutions with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2017/0140933 A1; “Lee”) or Lee (U.S. 2017/0140933 A1; “Lee”) in view of Hung et al. (U.S. 2023/0065195 A1; “Hung”) as applied to claim 1 above, and further in view of Ching et al. (U.S. 2017/0141112 A1; “Ching”).
Regarding claims 6 and 8, Lee discloses first source or drain structures at ends of the first vertical arrangement of semiconductor nanowires and second source or drain structures at ends of the second vertical arrangement of semiconductor nanowires ([0024]) but does not disclose the first source or drain structures and the second source or drain structures are epitaxially formed. However, Ching discloses non-discrete source or drain structures (835, Fig. 18B) at ends of a vertical arrangement of nanowire (316, Fig. 18B) which are epitaxially formed ([0045]). This has the advantage of forming high film quality source or drain structures. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lee or Lee in view of Hung with the source or drain structures at the ends of the semiconductor nanowires being epitaxial, as taught by Ching, so as to form high film quality source or drain structures.
Claim(s) 7 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2017/0140933 A1; “Lee”) or Lee (U.S. 2017/0140933 A1; “Lee”) in view of Hung et al. (U.S. 2023/0065195 A1; “Hung”) as modified by Ching et al. (U.S. 2017/0141112 A1; “Ching”) as applied to claim 6 above, and further in view of Balakrishnan et al. (U.S. 9,837,414 B1; “Balakrishnan”).
Regarding claim 7, Lee and Ching disclose epitaxial source or drain structures (see claim 6 rejection above) but do not disclose they are discrete structures. However, Balakrishnan discloses discrete epitaxial source and drain structures (col 10, lines 23-35). This has the advantage of forming a stacked device which advantageously increases chip density. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Lee or Lee in view of Hung and Ching with the epitaxial source and drain structures comprising discrete structures, as taught by Balakrishnan, so as to increase chip density.
Regarding claim 10, Lee and Ching disclose epitaxial source or drain structures (see claim 6 rejection above) but do not disclose a pair of conductive contact structures coupled to the source or drain structures. However, Balakrishnan discloses a pair of conductive contact structures (86, 98, Fig. 17) coupled to source or drain structures (col 14, lines 13-16; col 15, lines 4-15). This has the advantage of forming electrical connections to the source and drain structures. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Lee or Lee and Hung and Ching with a pair of conductive contact structures, as taught by Balakrishnan, so as to form electrical connections to the source and drain structures.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2017/0140933 A1; “Lee”) or Lee (U.S. 2017/0140933 A1; “Lee”) in view of Hung et al. (U.S. 2023/0065195 A1; “Hung”) as modified by Ching et al. (U.S. 2017/0141112 A1; “Ching”) as applied to claim 6 above, and further in view of Bi et al. (U.S. 2018/0190545 A1; “Bi”).
Regarding claim 9, Lee and Ching disclose gate stacks (Lee: 124, 128, Fig. 1J; [0027], [0034]) but do not disclose the gate stacks each comprise dielectric sidewall spacers. However, Bi discloses a gate stack comprising dielectric sidewall spacers such that the source or drain structures extend beneath the dielectric sidewall spacers ([0027], [0036]). This has the advantage of reducing leakage current. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Lee or Lee in view of Hung and Ching with the first gate stack and the second gate stack each comprising dielectric sidewall spacers, as taught by Bi, so as to reduce leakage current.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2017/0140933 A1; “Lee”) or Lee (U.S. 2017/0140933 A1; “Lee”) in view of Hung et al. (U.S. 2023/0065195 A1; “Hung”) as applied to claim 1 above, and further in view of Guha et al. (U.S. 2019/0393352 A1; “Guha”).
Regarding claim 12, Lee discloses a first gate stack (124, Fig. 1J) and a second gate stack (128, Fig. 1J) ([0027], [0034]) but does not disclose a gate endcap isolation structure. However, Guha discloses a gate endcap isolation structure between and in contact with a first gate stack and a second gate stack ([0048], [0051]; Fig. 5(c)). This has the advantage of shrinking the transistor layout to increase chip density. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lee or Lee in view of Hung with a gate endcap isolation structure between and in contact with the first gate stack and the second gate stack, as taught by Guha, so as to increase chip density.
Claim(s) 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2017/0140933 A1; “Lee”) in view of Hung et al. (U.S. 2023/0065195 A1; “Hung”) and Kim et al. (U.S. 2016/0211322 A1; “Kim”).
Regarding claim 14, Lee discloses an integrated circuit structure, comprising:
A first vertical arrangement of semiconductor nanowires (123, Fig. 1J) and a second vertical arrangement of semiconductor nanowires (125, Fig. 1J) above a substrate (102, Fig. 1J), the first vertical arrangement of semiconductor nanowires (123, Fig. 1J) having a greater number of semiconductor nanowires than the second vertical arrangement of semiconductor nanowires (125, Fig. 1J), the first (123, Fig. 1J) and second (125, Fig. 1J) vertical arrangements of semiconductor nanowires having uppermost semiconductor nanowires in a same horizontal plane, and the first vertical arrangement of semiconductor nanowires (123, Fig. 1J) having a bottommost semiconductor nanowire below a bottommost semiconductor nanowire of the second arrangement of semiconductor nanowires (125, Fig. 1J) ([0021]);
An oxide structure (“interfacial layer”) vertically beneath the bottommost semiconductor nanowire of the second arrangement of semiconductor nanowires (125, Fig. 1J), wherein the bottommost semiconductor nanowire of the second arrangement of semiconductor nanowires is vertically overlapping with the oxide structure along a vertical axis ([0035]: “like the gate structure 124, gate structure 128 may include an interfacial layer, a high-k dielectric layer, and a metal gate layer” in conjunction with [0019]: “interfacial layer may wrap around and contact each side of the elongated semiconductor materials” and “the interfacial layer may include an oxide-containing material….”) and the oxide structure (“interfacial layer”) is in a same horizontal plane as the bottommost semiconductor nanowire of the first vertical arrangement of semiconductor nanowires (since the bottommost semiconductor nanowire of the second vertical arrangement of semiconductor nanowires 125 at least partially laterally overlaps the bottommost semiconductor of the first vertical arrangement of semiconductors 123, an interfacial layer contacting each side of the bottommost semiconductor nanowire of the second vertical arrangement of semiconductor nanowires 125 would necessarily be partially in at least a same horizontal plane as a portion of the bottommost semiconductor of the first vertical arrangement of semiconductors 123);
A first gate stack (124, Fig. 1J) over the first vertical arrangement of semiconductor nanowires (123, Fig. 1J) ([0027]); and
A second gate stack (128, Fig. 1J) over the second vertical arrangement of semiconductor nanowires (125, Fig. 1J) and over the oxide structure ([0034]-[0035], [0019]; though not illustrated, the interfacial layer of the second gate stack is formed like the first gate stack ([0035]), wherein the interfacial layer is formed first and wraps arounds and contacts each side of the elongated semiconductor materials ([0019]) and wherein the metal gate layer wraps around each side of the elongated semiconductor features ([0034]). If the metal gate layer [of the second gate stack] wraps around each side of the elongated semiconductor features, wherein the interfacial layer wraps around and contacts each side of the elongated semiconductor features but is formed first, then the metal gate layer would necessarily wrap around and be over and contact each side of the interfacial layer).
Alternatively, assuming arguendo that the description in Lee does not implicitly illustrate the oxide structure (“interfacial layer”) vertically beneath the bottommost semiconductor nanowire of the second arrangement of semiconductor nanowires wherein the bottom nanowire of the second arrangement of semiconductor nanowires is vertically overlapping with the oxide structure along a vertical axis, and the oxide structure is in a same horizontal plane as the bottommost semiconductor nanowire of the first vertical arrangement of semiconductor nanowires, Hung discloses an oxide structure (260, Fig. 25) vertically beneath (portion of 260 under 216, Fig. 25) the bottommost semiconductor nanowire (bottommost 216, Fig. 25) of an arrangement of semiconductor nanowires. Hung further discloses a gate stack (290, Fig. 25) over the vertical arrangement of semiconductor nanowires (216, Fig. 25) and over the oxide structure (260, Fig. 25). This has the advantage of enhanced gate control and reduced leakage current.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lee with the oxide structure such that the second gate stack is over and around the second vertical arrangement of semiconductor nanowires and over and around the oxide structure, as taught by Hung, so as to enhance gate control and reduce leakage current.
As to the limitation the oxide structure (“interfacial layer”) is in a same horizontal plane as the bottommost semiconductor nanowire of the first vertical arrangement of semiconductor nanowires, since according to Lee the bottommost semiconductor nanowire of the second vertical arrangement of semiconductor nanowires (Lee: 125, Fig. 1J) at least partially laterally overlaps the bottommost semiconductor of the first vertical arrangement of semiconductors (Lee: 123, Fig. 1J), an interfacial layer, as taught by Hung, contacting each side of the bottommost semiconductor nanowire of the second vertical arrangement of semiconductor nanowires would necessarily be partially in at least a same horizontal plane as a portion of the bottommost semiconductor of the first vertical arrangement of semiconductors.
Yet, Lee does not disclose the integrated circuit structure is incorporated into a component coupled to a board. However, Kim discloses disclose an integrated circuit structure is incorporated into a component coupled to a board ([0031]). This has the advantage of forming parts of a computing device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lee with the integrated circuit incorporated into a component, as taught by Kim, so as to form a computing device.
Regarding claim 15, Kim discloses a memory coupled to the board to form the computing device ([0032]).
Regarding claim 16, Kim discloses a communication chip coupled to the board to form the computing device ([0032]).
Regarding claim 17, Kim discloses a battery coupled to the board to form the computing device ([0032]).
Regarding claim 18, Kim discloses a camera coupled to the board to form the computing device ([0032]).
Regarding claim 19, Kim discloses the component is a packaged integrated circuit die ([0034]).
Regarding claim 20, Kim discloses the component is a processor ([0031], [0034]).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 2-20 have been considered but are moot in view of the new ground(s) of rejection. Even with the new ground(s) of rejection, Examiner addresses Applicant’s arguments with respect to amended claims 1 and 14 to correct a mischaracterization of Examiner’s previous interpretation and clarify Examiner’s current interpretation.
Claim 1 was and is rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Lee et al. (U.S. 2017/0140933 A1; “Lee”) in view of Hung et al. (U.S. 2023/0065195 A1; “Hung”). Claim 14 was and is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2017/0140933 A1; “Lee”) in view of Hung et al. (U.S. 2023/0065195 A1; “Hung”) and Kim et al. (U.S. 2016/0211322 A1; “Kim”).
Applicant states that claims 1 and 14 have been amended with the subject matter that the bottommost semiconductor nanowire of the second arrangement of semiconductor nanowires is “vertically overlapping” with the oxide structure along a vertical axis (Remarks, pp 10-12). Applicant argues that this feature is not taught by the Lee reference because Examiner has alleged that “a trench isolation structure 116 reads on Applicant’s claimed “oxide structure”” and the nanowire stacks 123 or 125 therefore do not “vertically overlap” with the oxide structure (Remarks, pp 10-13).
Examiner responds by pointing out that Applicant is incorrect as to Examiner’s characterization of the “oxide structure” as it pertains to the most recent Office Action (Non-Final Rejection, 11/10/25). In the most recent Office Action (Non-Final Rejection, 11/10/25), Examiner interpreted the interfacial layer described within Lee ([0035]) as reading on or correlating to Applicant’s “oxide structure” (pp 10). Furthermore, Examiner notes that in this Office Action, the “interfacial layer” of Lee is again interpreted as correlating to Applicant’s “oxide structure”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/REEMA PATEL/Primary Examiner, Art Unit 2812 4/22/2026
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