Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims are rejected specifically in view of the limitation “forming a second photoresist layer by second coating and baking the high transmittance photoresist on the first photoresist layer;
forming a third photoresist layer by third coating and baking the high transmittance photoresist on the second photoresist layer” in claim 11.
A person having ordinary skills in the art will find the claim indefinite because it is unclear how the high transmittance photoresist that was coated and baked to form the first photoresist layer, is then coated and baked to form the second and third photoresist layers.
It is unclear whether the use of the limitation “the high transmittance photoresist” in the forming steps of the second and third photoresist layer is a typographical error, wherein what is intended is that in the forming of the second and third photoresist layer, respective the high transmittance photoresist was used.
Or if it intended that “the high transmittance photoresist” used in the forming of the second and third photoresist layer is a same material type used to form the first photoresist layer (which is supported by the specification of the application).
For examination purpose, the claimed limitation will be understood as respective high transmittance photoresist was used in forming the first, second and third photoresist layers.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Koike et al. [US PGUB 20190363041] in view of Lee et al. [US PGPUB 20210090973] with support from Cheng et al. [US PGUB 20220320029] (hereinafter Koike, Lee and Cheng).
Regarding claim 1, Koike teaches a method of manufacturing a semiconductor package, the method comprising:
forming a first wiring structure (structure of Fig. 3C exclude wafer 101, Fig. 3A), comprising a plurality of first wiring patterns (102/104/105/108/109, Para 67) that comprise a plurality of first connection pads (109, Fig. 3A), and a first insulation layer (103/106/107, Para 54-55) surrounding the plurality of first wiring patterns (Fig. 3A), the first wiring structure comprising a chip mounting region (region where chip 114 would be mounted, Fig. 3A/3H, Para 61) and a peripheral region adjacent to the chip mounting region (region where the chip would not be placed, Fig. 3A/3H);
coating a high transmittance photoresist (110/111, Para 57) on the first wiring structure (Fig. 3D) a plurality of number of times (Para 57);
forming a plurality of openings (112, Para 58) in the peripheral region by exposing and developing the high transmittance photoresist (Para 58);
forming a plurality of conductive posts (113, Para 59) connected to the plurality of first connection pads in the peripheral region by filling the plurality of openings with a conductive material (Para 59);
removing the high transmittance photoresist (Para 60, Fig. 3G);
disposing a semiconductor chip (114, Para 61) in the chip mounting region on the first wiring structure (Fig. 3H);
forming an encapsulant (115, Para 62) surrounding the semiconductor chip and the plurality of conductive posts (Fig. 3I); and
wherein light transmittance of the high transmittance photoresist is equal to or greater than 3.2% at a portion where the first wiring structure contacts the high transmittance photoresist (Para 31, i.e., 100% for the desired purpose to effectively form the opening).
Koike does not specifically disclose forming a second wiring structure on the encapsulant, the second wiring structure comprising a plurality of second wiring patterns that comprise a plurality of second connection pads electrically connected to the plurality of conductive posts and a second insulation layer surrounding the plurality of second wiring patterns.
However, it is note that Koike discloses forming solder terminal 118 on the surface of post 113 (Para 64, Fig. 5).
In view of such further teaching by Koike, a person having ordinary skills in the art will understand that the formation of solder terminal 118 on the surface of post 113 is for the purpose of attaching of the structure of Fig. 3I/5 to another component.
Referring to the invention of Lee (with support from Fig. 9 of Cheng), Lee teaches mounting package P2 on package P1 via second wiring structure (see annotated Fig. 2H) on an encapsulant 130 (Fig. 2H), the second wiring structure comprising a plurality of second wiring patterns (Fig. 2H; i.e., the pads in the wiring structure connected to bonding wires of package P2 and pads connected to solder terminal 160) that comprise a plurality of second connection pads electrically connected to the plurality of conductive posts (100′, Para 53, Fig. 2G/H) and a second insulation layer (Fig. 2H, i.e., material in which the second wiring patterns are formed) surrounding the plurality of second wiring patterns (see annotated Fig. 2H).
Regarding claim 2, Koike teaches a method wherein, in the coating of the high transmittance photoresist a number of times (Para 57), a thickness of the high transmittance photoresist is at least 120 µm (where photoresist 110 by itself is 120 µm (Para 57)).
The modified invention of Koike does not explicitly disclose that a total thickness of the high transmittance photoresist is 260 µm to 500 µm.
However, it is noted that Koike depicts high transmittance photoresists 110 and 111 to have similar height, thus, a person having ordinary skills in the art would find it obvious that the total high transmittance photoresist be at about 240 µm.
In view of such analysis/rationale, it should be noted that a prima facie case of obviousness seems to exists, since it has held that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness is deemed to exists (MPEP 2144.05.I).
Moreover, Cheng discloses an exemplary thickness of high transmittance photoresist 301 in which conductive post 303 are formed to be between about 30 μm and about 350 μm, such as about 200 μm. However, any suitable thickness may alternatively be used (Para 34).
In view of such teaching by Cheng, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to determine the optimum thickness (for the desired device structure) of the high transmittance photoresist used in the manufacturing process –wherein the thickness could depend on thickness of the mounted chip and/or desired clearance from the mounted chip.
Regarding claim 4, the modified invention of Koike teaches the method of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein the high transmittance photoresist comprises a negative photoresist.
Referring to the invention of Cheng, Cheng teaches a method wherein the high transmittance photoresist comprises a positive of negative photoresist (Para 31; developer is then applied to the exposed third photoresist 301 to take advantage of the physical changes and selectively remove either the exposed portion of the third photoresist 301 or the unexposed portion of the third photoresist 301, depending upon the desired pattern, and form the desired pattern for the through vias 303).
In view of such teaching by Cheng, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the high transmittance photoresist comprises a negative photoresist at least based on the rationale of simple substitution of one known method with a suitable another to obtain predictable results (MPEP 2143.I.B) or using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Regarding claim 6, Koike teaches a method wherein, in the forming of the plurality of conductive posts, the plurality of openings are all filled with the conductive material through a single plating process (Para 59 –i.e., electroplating is used without other plating process).
Claims 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee with support from Cheng.
Regarding claim 16, Lee teaches a semiconductor package comprising:
a first redistribution structure (140, Para 30, Fig. 2G/H) comprising:
a plurality of first redistribution patterns (Para 30, Fig. 2G/H) comprising a plurality of first bottom surface connection pads (pad connected to conductive terminals 150, Para 30, Fig. 2G/H) and a plurality of first top surface connection pads (pads connected to portion 100b, Fig. 2G/H); and
a first redistribution insulation layer (Para 30) surrounding the plurality of first redistribution patterns (Fig. 2G/H);
a first semiconductor chip (110, Para 30) on a first chip mounting region on the first redistribution structure (Fig. 2G/H);
a second redistribution structure (see annotated Fig. 2H) on the first semiconductor chip and the first redistribution structure (Fig. 2H), the second redistribution structure comprising:
a plurality of second redistribution patterns (see annotated Fig. 2H) comprising a plurality of second bottom surface connection pads (see annotated Fig. 2H) and a plurality of second top surface connection pads (see annotated Fig. 2H); and
a second redistribution insulation layer (see annotated Fig. 2H –with support from Fig. 9 of Cheng) surrounding the plurality of second redistribution patterns (Fig. 2H);
a second semiconductor chip (see annotated Fig. 2H) on a second chip mounting region on the second redistribution structure (see annotated Fig. 2H);
a plurality of conductive posts (100′, Para 53) adjacent to the first semiconductor chip (Fig. 2H) and connecting some of the plurality of first top surface connection pads to some of the plurality of second bottom surface connection pads (Fig. 2G); and
an encapsulant (130, Para 50) filling a space between the first redistribution structure and the second redistribution structure and surrounding the plurality of conductive posts and the first semiconductor chip (Fig. 2H),
wherein each of the plurality of conductive posts comprises:
a body portion (100a, Fig. 2G) having a constant horizontal cross-sectional area (Fig. 2G); and
a bottom portion (100b′ Fig. 2G) having a varying horizontal cross-sectional area (Fig. 2G), and
wherein a top surface of the body portion has a first diameter and a bottom surface of the bottom portion has a second diameter that is different from the first diameter (Fig. G/H).
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Annotated Fig. 2H
Regarding claim 19, Lee teaches a semiconductor package wherein a rate of change of the horizontal cross-sectional area of the bottom portion in a vertical direction is constant (Fig. 2H, i.e., the change continues to increase through the height of the bottom portion without a decrease).
Regarding claim 20 Lee as applied in the rejection of claim 16 teaches the limitation of claim 16.
Lee as applied in the rejection of claim 16 does not teaches wherein a rate of change of the horizontal cross-sectional area of the bottom portion in a vertical direction decreases in a direction toward the first redistribution structure.
Referring to the embodiment of Fig. 3B, Lee teaches an alternate structure to that of Fig. 2H, wherein an implementation of the structure of Fig. 3B in Fig. 2H would result in a rate of change of the horizontal cross-sectional area of the bottom portion in a vertical direction decreases in a direction toward the first redistribution structure.
In view of such teaching by Lee according to Fig. 3B, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the embodiment of Fig. 2H have the post structure of Fig. 3B at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Koike in view of Lee with support from Cheng and further in view of Kim et al. [US PGUB 20090215346] (hereinafter Kim).
Regarding claim 11. Koike teaches a method of manufacturing a semiconductor package, the method comprising:
forming a first wiring structure (structure of Fig. 3C exclude wafer 101, Fig. 3A) comprising a chip mounting region (region where chip 114 would be mounted, Fig. 3A/3H, Para 61) and a peripheral region (region where the chip would not be placed, Fig. 3A/3H) adjacent to the chip mounting region (Fig. 3H);
forming a first photoresist layer (110, Para 57) by first coating (Fig. 3D; wherein the providing of the first photoresist layer is a coating process) a high transmittance photoresist on the first wiring structure (Fig. 3D);
forming a second photoresist layer (111, Para 57) by second coating (Fig. 3D; wherein the providing of the first photoresist layer is a coating process) the high transmittance photoresist on the first photoresist layer (Fig. 3D);
forming a plurality of openings (112, Para 58) in the peripheral region by exposing and developing the first photoresist layer and the second photoresist layer (Para 58);
forming a plurality of conductive posts (113, Para 59) by filling the plurality of openings with a conductive material through a single plating process (Para 59 –electroplating);
removing the first photoresist layer and the second photoresist layer (Para 60, Fig. 3G);
disposing a semiconductor chip (114, Para 61) in the chip mounting region on the first wiring structure (Fig. 3H);
forming an encapsulant (115, Para 62) surrounding the semiconductor chip and the plurality of conductive posts (Fig. 3I); and
wherein light transmittance of the first photoresist layer is greater than or equal to 3.2% at a portion where the first wiring structure contacts the first photoresist layer (Para 31, i.e., 100% for the desired purpose to effectively form the opening).
Koike does not specifically disclose forming a first photoresist layer by baking;
forming a second photoresist layer by baking;
forming a third photoresist layer by third coating and baking the high transmittance photoresist on the second photoresist layer;
forming a plurality of openings in the peripheral region by exposing and developing the third photoresist layer;
removing the third photoresist layer; and
forming a second wiring structure on the encapsulant.
However, it is noted the Koike discloses the idea of a third electrode part which is formed by forming a third photoresist layer (Para 87). In view of such disclosure, a person having ordinary skills in the art will find it obvious that Koike is suggesting that the height of the conductive post of the invention can be increased if so desired.
Thus, it seems reasonable that before the effective filing date of the claimed invention that a person having ordinary skills in the art will consider a formation process of the embodiment of Fig. 3 further comprising a third photoresist coated on the second photoresist, forming a plurality of openings in the peripheral region by exposing and developing the third photoresist layer; and removing the third photoresist layer –such a conclusion at least based on the rationale of relying on teachings, suggestions, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G).
It is noted that Koike further discloses forming solder terminal 118 on the surface of post 113 (Para 64, Fig. 5).
In view of such further teaching by Koike, a person having ordinary skills in the art will understand that the formation of solder terminal 118 on the surface of post 113 is for the purpose of attaching of the structure of Fig. 3I/5 to another component.
Referring to the invention of Lee (with support from Fig. 9 of Cheng), Lee teaches mounting package P2 on package P1 via second wiring structure (see annotated Fig. 2H) on an encapsulant 130 (Fig. 2H).
In view of such teaching by Lee, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Koike comprise the teachings of Lee in order to form a more multifaceted device.
Referring to the invention of Kim, Kim discloses a method of providing photoresist material, wherein the process comprises the spin coating photo-resist on a substrate and then, the photo-resist is soft-baked to dry out excessive solvent in the photo-resist (Para 25).
In view of such teaching by Kim, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the photoresist of Koike formed as taught by Kim at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
In view of modification of Koike’s disclosure for the embodiment of Fig. 3, it would be obvious to a person having ordinary skills in the art that the limitations of claim 11 would be met.
Regarding claim 12, Koike teaches a method wherein the first photoresist layer 110 has a thickness of at least 120 µm (Para 57).
The modified invention of Koike does not explicitly disclose that a total thickness of the first photoresist layer, the second photoresist layer, and the third photoresist layer is 260 µm to 500 µm.
However, it is noted that Koike depicts photoresists layers 110 and 111 to have similar height, thus, a person having ordinary skills in the art would find it obvious that the total high transmittance photoresist be at about 240 µm. With the introduction of a third photoresist layer (where the third photoresist would be similar to the first and second photoresist), is would be obvious that the total thickness of the first, second, and third photoresist would be about 360 µm.
In view of such analysis/rationale, it should be noted that a prima facie case of obviousness seems to exists, since it has held that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness is deemed to exists (MPEP 2144.05.I).
Moreover, Cheng discloses an exemplary thickness of high transmittance photoresist 301 in which conductive post 303 are formed to be between about 30 μm and about 350 μm, such as about 200 μm. However, any suitable thickness may alternatively be used (Para 34).
In view of such teaching by Cheng, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to determine the optimum thickness (for the desired device structure) of the high transmittance photoresist used in the manufacturing process –wherein the thickness could depend on thickness of the mounted chip and/or desired clearance from the mounted chip.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Koike in view of Lee with support from Cheng and further in view of Kim and Wang et al. [US PGUB 20240079307] (hereinafter Wang).
Regarding claim 3, Koike teaches a method wherein the coating of the high transmittance photoresist the plurality of number of times comprises:
first coating a first high transmittance photoresist (110, Para 57) on the first wiring structure (Fig. 3D);
second coating a second high transmittance photoresist (111, Para 57) on the first high transmittance photoresist (Fig. 3D).
The modified invention does not specifically disclose baking the first high transmittance photoresist;
baking the second high transmittance photoresist;
third coating and baking a third high transmittance photoresist on the second high transmittance photoresist,
wherein the first high transmittance photoresist, the second high transmittance photoresist, and the third high transmittance photoresist comprise a same photoresist material.
However, it is noted the Koike discloses the idea of a third electrode part which is formed by forming a third photoresist layer (Para 87). In view of such disclosure, a person having ordinary skills in the art will find it obvious that Koike is suggesting that the height of the conductive post of the invention can be increased if so desired.
Thus, it seems reasonable that before the effective filing date of the claimed invention that a person having ordinary skills in the art will consider a formation process of the embodiment of Fig. 3 further comprising third coating a third high transmittance photoresist on the second high transmittance photoresist –such a conclusion at least based on the rationale of relying on teachings, suggestions, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G).
Referring to the invention of Kim, Kim discloses a method of providing photoresist material, wherein the process comprises the spin coating photo-resist on a substrate and then, the photo-resist is soft-baked to dry out excessive solvent in the photo-resist (Para 25).
In view of such teaching by Kim, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the photoresist of Koike formed as taught by Kim at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Referring to the invention of Wang, teaches the use of photoresist layer in the form of conductive post, wherein the photoresist used can be more or less than 3 photoresist layer and wherein the photoresist layers have different characteristics. In certain instance, photoresist layers 710-730 are used in the forming of conductive posts 232, and wherein the photoresist a made of negative photoresist material (Para 49-50).
In view of such teaching by Wang, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Koike comprise the teaching of Wang (using photoresist layer of same material) at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Allowable Subject Matter
Claims 5, 7-10 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-15 are not rejected in view of a prior art considered possibly allowable. The certainty of their allowability is unclear because of the rejection of claim 11 under35 U.S.C. 112(b).
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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