DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/19/2023 and 3/18/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1 recites the limitation “wherein each of the semiconductor stacks is stacked by a well layer and a barrier layer” (emphasis added) in lines 8-9 of the claim, which is unusual wording and thus the Examiner suggests amending the limitation to either “wherein each of the semiconductor stacks comprises a well layer and a barrier layer” or “wherein each of the semiconductor stacks includes a well layer and a barrier layer”.
Claim 1 recites the limitation “the first confinement layer or the second confinement layer includes a different material as the light emitting structure” (emphasis added) in lines 17-18 of the claim, which is unusual wording and thus the Examiner suggests amending the limitation to “the first confinement layer or the second confinement layer includes a different material than the light emitting structure”.
Claim 1 recites the limitation “the first cladding layer include a ternary semiconductor material” (emphasis added) in lines 18-19 of the claim, which appears to be grammatically incorrect and thus the Examiner suggests amending the limitation to “the first cladding layer includes a ternary semiconductor material”.
Appropriate correction is required.
Note the dependent claims 2-20 necessarily inherit the objected subject matter of the claims on which they depend.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “a range” in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation “the thickness of the second confinement layer” in lines 3-4 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the objected subject matter and/or the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding independent claim 1, Tsuda et al. (US 2005/0095768 A1, hereinafter “Tsuda”) discloses a semiconductor device, comprising:
a first semiconductor structure 104/105 comprising a first confinement layer 105 (“light guide layer”- ¶0099) and a first cladding layer 104 (“clad layer”- ¶0099) adjacent to the first confinement layer 105;
a second semiconductor structure 108 (“light guide layer”- ¶0099) located on the first semiconductor structure 104/105 and comprising a second confinement layer 108; and
a light-emitting structure 106 (“light emitting layer”- ¶0099) located between the first semiconductor structure 104/105 and the second semiconductor structure 108, and including a first multiple quantum well structure (“quantum well structure”- ¶0156) containing a plurality of semiconductor stacks, wherein each of the semiconductor stacks is stacked by a well layer (i.e., “well layer”- ¶0158) and a barrier layer (i.e., “barrier layer”- ¶0158) (¶¶0154-0159);
wherein the first confinement layer 105 and the second confinement layer 108 are adjacent to the light emitting structure 106, the well layer comprises a quaternary semiconductor material comprising InGaAsP, AlGaInAs or InGaNAs, the well layer has a first In content percentage (¶0158); and
wherein the first confinement layer 105 or the second confinement layer 108 includes a different material as the light emitting structure (¶¶0099, 0158), and the first cladding layer 104 include a ternary semiconductor material (¶0099).
Tsuda does not disclose wherein the well layer and the barrier layer in each of the semiconductor stacks comprise the same quaternary semiconductor material comprising InGaAsP, AlGaInAs or InGaNAs, the well layer has a first In content percentage, and the barrier layer has a second In content percentage less than the first In content percentage and wherein the light-emitting structure emits an incoherent light having a peak wavelength in a range of 700 nm to 3000 nm
Thus, regarding independent claim 1 (which claims 2-20 depend from), the prior art of record including Tsuda, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “the well layer and the barrier layer in each of the semiconductor stacks comprise the same quaternary semiconductor material comprising InGaAsP, AlGaInAs or InGaNAs, the well layer has a first In content percentage, and the barrier layer has a second In content percentage less than the first In content percentage” and “wherein the light-emitting structure emits an incoherent light having a peak wavelength in a range of 700 nm to 3000 nm”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Tsuda et al. (US 2004/0026710 A1), which discloses a semiconductor device comprising a light-emitting structure including a barrier layer formed of a quaternary semiconductor material comprising InGaAsP, AlGaInAs or InGaNAs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C CHANG/ Primary Examiner, Art Unit 2817