DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 02/12/2026. Claims 1-23 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 10/20/2023 is acceptable.
Election/Restrictions
Applicant hereby elects group I and species M.I. “The claims readable upon the elected group are claims 1-14, drawn to a non-volatile memory device and described in Figs. 1-4. Claims 15-23 and species M.II (a semiconductor device as described in Fig. 5) are withdrawn without prejudice or disclaimer to the merits”, in the “Response to Election / Restriction Filed” filed on 02/12/2026 is acknowledged. This office action considers claims 1-23 are thus pending for prosecution of which, non-elected claims 15-23 are withdrawn, and elected claims 1-14 are examined on their merits.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 7-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 2016/0336415 A1; hereafter Wu) in view of Ruttkowski et al (US 2008/0285344 A1; hereafter Ruttkowski).
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Regarding claim 1. Wu discloses a non-volatile memory device, comprising at least one memory cell, wherein the at least one memory cell comprises:
a substrate (Fig.[1A], substrate 108);
a select gate (Fig.[1A], word lines 136A, construed as select gate) disposed on the substrate (Fig.[1A], substrate 108);
a control gate (Fig.[1A], control gates 120A) disposed on the substrate (Fig.[1A], substrate 108) and laterally spaced apart from the select gate (Fig.[1A], word lines 136A, construed as select gate), wherein the control gate (Fig.[1A], control gates 120A) comprises a non-vertical surface (Fig.[1A], control gates 120A, bottom surface);
planar floating gate (Fig.[1A], Floating gates 114A) disposed between the substrate (Fig.[1A], substrate 108) and the control gate (Fig.[1A], control gates 120A), wherein the planar floating gate (Fig.[1A], Floating gates 114A) comprises a lateral tip (Fig.[1A], Floating gates 114A, right corner) laterally spaced apart from the control gate (Fig.[1A], control gates 120A);
a coupling dielectric layer (Fig.[1A], gate dielectric layer 122A, Para [ 0028]) disposed between the control gate (Fig.[1A], control gates 120A) and the planar floating gate (Fig.[1A], Floating gates 114A), wherein the coupling dielectric layer comprises a first thickness (Fig.[1A], gate dielectric layer 122A, construed as first thickness, Para [ 0028]);
an erase gate dielectric layer (Fig.[1A], tunneling dielectric layers 134A) covering the non-vertical surface of the control gate (Fig.[1A], control gates 120A) and the lateral tip of the planar floating gate (Fig.[1A], Floating gates 114A, right corner), wherein the erase gate dielectric layer comprises a second thickness (tunneling dielectric layers 134A, construed as second thickness); and
an erase gate (Fig.[1A], erase gate 130) covering the erase gate dielectric layer (Fig.[1A], tunneling dielectric layers 134A) and the lateral tip of the planar floating gate (Fig.[1A], Floating gates 114A).
But Wu does not disclose explicitly wherein the first thickness and the second thickness satisfy the following relation:(T2) < (T1)< 2(T2) wherein T1 represents the first thickness of the coupling dielectric layer, and T2 represents the second thickness of the erase gate dielectric layer.
In a similar field of endeavor, Ruttkowski discloses “The tunnel dielectric layer 504 may have a layer thickness of at least 6 nm, for example, 6 nm to 120 nm or greater”, (Para [ 0113]) and “the thickness of the remaining first gate dielectric layer 2014 is increased to a thickness of about 8 nm”, (Para [ 0164]). In addition, Para [0229] discloses “the tunnel dielectric layer 2804 and the gate dielectric layer 2824 may be made of silicon oxide and with a physical thickness in the range of about 3 nm to about 10 nm, e.g., a physical thickness of 8 nm (in an embodiment of the invention, the equivalent oxide thickness (EOT) of these layers may be about 10 nm) “. Therefore, based on the thickness variation, first thickness and second thickness, can satisfy following relation:(T2) < (T1)< 2(T2) wherein T1 represents the first thickness of the coupling dielectric layer, and T2 represents the second thickness of the erase gate dielectric layer.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Wu in light of Ruttkowski teaching to modify Wu first and second thickness for further advantage such as to reduce leakage current between the word line and the floating gate leading to the increase in the thickness of the dielectric region between the erase gate and the floating gate, thus exhibiting improved reliability and improved device performance.
Regarding claim 2. Wu and Ruttkowski disclose the non-volatile memory device of claim 1, Wu further disclose the wherein the non-vertical surface of the control gate (Fig.[1A], control gates 120A, bottom surface) comprises an inclined surface or a curved surface (Fig.[1A], control gates 120A, bottom surface).
Regarding claim 3. Wu and Ruttkowski disclose the non-volatile memory device of claim 1, Wu further disclose wherein the planar floating gate (Fig.[1A], Floating gates 114A) further comprises:
two first sidewalls opposite each other and arranged along a first direction (Fig.[1A], Floating gates 114A, two lateral ends), wherein one of the first sidewalls (Fig.[1A], Floating gates 114A, right lateral ends) is connected to the lateral tip (Fig.[1A], Floating gates 114A, right corner); and
two second sidewalls opposite each other and arranged along a second direction different from the first direction (Fig.[1A], Floating gates 114A, upper/ lower surfaces), wherein the control gate (Fig.[1A], control gates 120A) extends along the second direction and covers the two second sidewalls of the planar floating gate (Floating gates 114A).
Regarding claim 7. Wu and Ruttkowski disclose the non-volatile memory device of claim 1, Wu further disclose wherein the coupling dielectric layer (Fig.[1A], gate dielectric layer 122A, Para [ 0028]) comprises a curved sidewall covered with the control gate (Fig.[1A], control gates 120A).
Regarding claim 8. Wu and Ruttkowski disclose the non-volatile memory device of claim 7, Wu further disclose wherein a portion of the erase gate dielectric layer (Fig.[1A], tunneling dielectric layers 134A) is disposed between the control gate (Fig.[1A], control gates 120A) and the planar floating gate (Fig.[1A], Floating gates 114A).
Regarding claim 9. Wu and Ruttkowski disclose the non-volatile memory device of claim 7, Wu further disclose wherein the erase gate comprises a protruding portion (Fig.[1A], erase gate 130) extending toward the curved sidewall of the coupling dielectric layer (Fig.[1A], gate dielectric layer 122A, Para [ 0028]).
Regarding claim 10. Wu and Ruttkowski disclose the non-volatile memory device of claim 1, Wu further disclose wherein the erase gate (Fig.[1A], erase gate 130) comprises a flat top surface (Fig.[1A], erase gate 130) covering the non-vertical surface of the control gate (Fig.[1A], control gates 120A).
Regarding claim 11. Wu and Ruttkowski disclose the non-volatile memory device of claim 1, Wu further disclose wherein the erase gate (Fig.[1A], control gates 120A) is laterally spaced apart from the select gate (Fig.[1A], word lines 136A, construed as select gate).
Regarding claim 12. Wu and Ruttkowski disclose the non-volatile memory device of claim 1, Wu further disclose wherein the at least one memory cell comprises a first memory cell and a second memory cell (Fig.[1A], memory cells 102A/102B, Para [ 0015]), each of the first memory cell and the second memory cell (Fig.[1A], memory cells 102A/102B, Para [ 0015]) comprising the select gate (Fig.[1A],136A/136B), the floating gate (Fig.[1A], 114A/114B) and the control gate ( Fig.[1A], 120A/120B), the non-volatile memory device further comprises a source region shared (common source/drain region 104 is a source region, Para [ 0016]) by the first memory cell and the second memory cell (Fig.[1A], memory cells 102A/102B, Para [ 0015]), and the source region (Fig.[1A], common source/drain region 104 is a source region, Para [ 0016]) is covered with the erase gate (Fig.[1A], erase gate 130).
Regarding claim 13. Wu and Ruttkowski disclose the non-volatile memory device of claim 10, Wu further disclose wherein the first memory cell and the second memory cell have a mirror image of each other (Fig.[1A], memory cells 102A/102B, Para [ 0015]).
Regarding claim 14. Wu and Ruttkowski disclose the non-volatile memory device of claim 10, Wu further disclose wherein the erase gate (Fig.[1A], erase gate 130) is filled into a gap between the control gates (Fig.[1A], control gates 120A/120B) of the first memory cell and the second memory cell (Fig.[1A], memory cells 102A/102B, Para [ 0015]).
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 4. The non-volatile memory device of claim 3, wherein the coupling dielectric layer extends along the second direction and covers the two second sidewalls of the planar floating gate.
Regarding claim 5. The non-volatile memory device of claim 1, wherein the coupling dielectric layer comprises:
a vertical portion disposed between the control gate and the select gate; and a horizontal portion disposed between the control gate and the planar floating gate, wherein the horizontal portion of the coupling dielectric layer comprises a curved sidewall.
Claims 6-7 is objected based on the dependency of claim 5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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