DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s reply filed on 07/17/2026 has been entered and considered. Applicants’ amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US 2016/0336415 A1; hereafter Wu) in view of Cheng et al (US 2015/0249158 A1; hereafter Cheng).
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Regarding claim 1. Wu discloses a non-volatile memory device, comprising at least one memory cell, wherein the at least one memory cell comprises:
a substrate (Fig.[1A], substrate 108);
a select gate (Fig.[1A], word lines 136A, construed as select gate) disposed on the substrate (Fig.[1A], substrate 108);
a control gate (Fig.[1A], control gates 120A) disposed on the substrate (Fig.[1A], substrate 108) and laterally spaced apart from the select gate (Fig.[1A], word lines 136A, construed as select gate), wherein the control gate (Fig.[1A], control gates 120A) comprises a non-vertical surface (Fig.[1A], control gates 120A, bottom surface);
planar floating gate (Fig.[1A], Floating gates 114A) disposed between the substrate (Fig.[1A], substrate 108) and the control gate (Fig.[1A], control gates 120A), wherein the planar floating gate (Fig.[1A], Floating gates 114A) comprises a lateral tip (Fig.[1A], Floating gates 114A, right corner) laterally spaced apart from the control gate (Fig.[1A], control gates 120A);
a coupling dielectric layer (Fig.[1A], gate dielectric layer 122A, Para [0028]) disposed between the control gate (Fig.[1A], control gates 120A) and the planar floating gate (Fig.[1A], Floating gates 114A), wherein the coupling dielectric layer comprises a first thickness (Fig.[1A], gate dielectric layer 122A, construed as first thickness, Para [ 0028]);
an erase gate dielectric layer (Fig.[1A], tunneling dielectric layers 134A) covering the non-vertical surface of the control gate (Fig.[1A], control gates 120A) and disposed over ( at least a portion, annotated) the lateral tip of the planar floating gate (Fig.[1A], Floating gates 114A, right corner), wherein the erase gate dielectric layer comprises a second thickness (tunneling dielectric layers 134A, construed as second thickness); and
an erase gate (Fig.[1A], erase gate 130) covering the erase gate dielectric layer (Fig.[1A], tunneling dielectric layers 134A) and the lateral tip of the planar floating gate (Fig.[1A], Floating gates 114A).
But Wu does not disclose explicitly wherein the first thickness and the second thickness satisfy the following relation:(T2) < (T1)< 2(T2) wherein T1 represents the first thickness of the coupling dielectric layer, and T2 represents the second thickness of the erase gate dielectric layer.
In a similar field of endeavor, Cheng discloses “gate dielectric between the erase gate and the control and floating gates. If a divot with about 200.ANG.-250 .ANG. depth is formed in the gate dielectric, a total thickness of the layer(s) that can be used as a protector of the floating gate during a following implantation process may be just 350 .ANG”, (Para [ 0029]). In addition, Para [0229] discloses “A total thickness t.sub.1 of the second gate dielectric 118 and the protective layer 138 may be equal to or larger than a total thickness t.sub.2 of the extending portion 106a of the first gate structure 106, so as to protect the protruding portion 110a from damaged by the following process steps in a better way. For example, the thickness of the protective layer 138 may be 200 .ANG. or more “. Therefore, based on the thickness variation in the gate dielectric layer, the following thickness condition can be optimize to in order to protect floating gate, erase gate and control gate such as “(T2) < (T1)< 2(T2), wherein T1 represents the first thickness of the coupling dielectric layer, and T2 represents the second thickness of the erase gate dielectric layer”.
It would have been obvious to one of ordinary skill in the art before the effective filing date to vary thickness of the coupling dielectric layer, and the erase gate dielectric layer, through routine experimentation, “(T2) < (T1)< 2(T2), wherein T1 represents the first thickness of the coupling dielectric layer, and T2 represents the second thickness of the erase gate dielectric layer” in order to optimize the functionality such as to protect floating gate, erase gate and control gate of the semiconductor device (see MPEP §2144.05).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Wu in light of Cheng teaching to modify Wu first and second thickness for further advantage such as protecting floating gate, erase gate and control gate of the semiconductor device and enhance device performance.
Regarding claim 2. Wu and Cheng disclose the non-volatile memory device of claim 1, Wu further disclose the wherein the non-vertical surface of the control gate (Fig.[1A], control gates 120A, bottom surface) comprises an inclined surface or a curved surface (Fig.[1A], control gates 120A, bottom surface).
Regarding claim 3. Wu and Cheng disclose the non-volatile memory device of claim 1, Wu further disclose wherein the planar floating gate (Fig.[1A], Floating gates 114A) further comprises:
two first sidewalls opposite each other and arranged along a first direction (Fig.[1A], Floating gates 114A, two lateral ends), wherein one of the first sidewalls (Fig.[1A], Floating gates 114A, right lateral ends) is connected to the lateral tip (Fig.[1A], Floating gates 114A, right corner); and
two second sidewalls opposite each other and arranged along a second direction different from the first direction (Fig.[1A], Floating gates 114A, upper/ lower surfaces), wherein the control gate (Fig.[1A], control gates 120A) extends along the second direction and covers the two second sidewalls of the planar floating gate (Floating gates 114A).
Regarding claim 8. Wu and Cheng disclose the non-volatile memory device of claim 7, Wu further disclose wherein a portion of the erase gate dielectric layer (Fig.[1A], tunneling dielectric layers 134A) is disposed between the control gate (Fig.[1A], control gates 120A) and the planar floating gate (Fig.[1A], Floating gates 114A).
Regarding claim 10. Wu and Cheng disclose the non-volatile memory device of claim 1, Wu further disclose wherein the erase gate (Fig.[1A], erase gate 130) comprises a flat top surface (Fig.[1A], erase gate 130) covering the non-vertical surface of the control gate (Fig.[1A], control gates 120A).
Regarding claim 11. Wu and Cheng disclose the non-volatile memory device of claim 1, Wu further discloses wherein the erase gate (Fig.[1A], control gates 120A) is laterally spaced apart from the select gate (Fig.[1A], word lines 136A, construed as select gate).
Regarding claim 12. Wu and Cheng disclose the non-volatile memory device of claim 1, Wu further disclose wherein the at least one memory cell comprises a first memory cell and a second memory cell (Fig.[1A], memory cells 102A/102B, Para [ 0015]), each of the first memory cell and the second memory cell (Fig.[1A], memory cells 102A/102B, Para [ 0015]) comprising the select gate (Fig.[1A],136A/136B), the floating gate (Fig.[1A], 114A/114B) and the control gate ( Fig.[1A], 120A/120B), the non-volatile memory device further comprises a source region shared (common source/drain region 104 is a source region, Para [ 0016]) by the first memory cell and the second memory cell (Fig.[1A], memory cells 102A/102B, Para [ 0015]), and the source region (Fig.[1A], common source/drain region 104 is a source region, Para [ 0016]) is covered with the erase gate (Fig.[1A], erase gate 130).
Regarding claim 13. Wu and Cheng disclose the non-volatile memory device of claim 10, Wu further disclose wherein the first memory cell and the second memory cell have a mirror image of each other (Fig.[1A], memory cells 102A/102B, Para [ 0015]).
Regarding claim 14. Wu and Cheng disclose the non-volatile memory device of claim 10, Wu further disclose wherein the erase gate (Fig.[1A], erase gate 130) is filled into a gap between the control gates (Fig.[1A], control gates 120A/120B) of the first memory cell and the second memory cell (Fig.[1A], memory cells 102A/102B, Para [ 0015]).
Allowable Subject Matter
Claims 4-7 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 4. The non-volatile memory device of claim 3, wherein the coupling dielectric layer extends along the second direction and covers the two second sidewalls of the planar floating gate.
Regarding claim 5. The non-volatile memory device of claim 1, wherein the coupling dielectric layer comprises:
a vertical portion disposed between the control gate and the select gate; and a horizontal portion disposed between the control gate and the planar floating gate, wherein the horizontal portion of the coupling dielectric layer comprises a curved sidewall.
Claim 6 is objected based on the dependency of claim 5.
Regarding claim 7. The non-volatile memory device of claim 1, wherein the coupling dielectric layer comprises a concave sidewall covered with the control gate.
Claims 9 is objected based on the dependency of claim 7
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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