DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 05/07/2026. Claims 1-26 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 10/27/2021.
Oath/Declaration
The oath or declaration filed on 10/20/2023 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/20/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Election/Restrictions
Applicant’s election, without traverse invention I, Species I, as depicted in FIGS. 1-3, with claims 1-20, in the “Response to Election / Restriction Filed” filed on 05/07/2026 is acknowledged and entered.
This office action considers claims 1-26 are thus pending for prosecution, of which, non-elected claims 21-26 are withdrawn, and elected claims 1-20 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al (US 2021/0399104 A1; hereafter Chang).
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Regarding claim 1. Chang discloses a semiconductor device (Fig 18 [A-C]) comprising:
a first transistor (Fig 18, transistor 200N, Para [ 0023]) on a first region of a substrate (Fig 18, substrate 202, Para [ 0035]); and
a second transistor (Fig 18, transistor 200P, Para [ 0023]) on a second region of the substrate (Fig 18, substrate 202), wherein the first transistor includes:
first semiconductor channel layers (Fig 18, channel layers 215, Para [ 0033]) spaced apart from each other and stacked (Fig 18, channel layers 215, Para [ 0033]) on the first region of the substrate in a vertical direction perpendicular to an upper surface of the substrate (Fig 18, substrate 202), a first gate insulating layer (Fig 18, stack [279n, 280], Para [0011, 0050]) surrounding the first semiconductor channel layers (channel layers 215, Para [ 0033]), and including a first interfacial insulating layer (Fig 18, interfacial layer 280, Para [ 0011]), a first lower high-k dielectric layer containing a first metal element (Fig 18, high-k dielectric layer 282, Para [ 0033]), and a first composite dielectric layer (Fig 18, high-k dielectric layer 284, Para [ 0041]) containing the first metal element and a second metal element different from the first metal element (high-k dielectric layer 284, Para [ 0041]), the first interfacial insulating layer (Fig 18, interfacial layer 280, Para [ 0011]), the first lower high-k dielectric layer (Fig 18, high-k dielectric layer 282, Para [ 0033]) and the first composite dielectric layer (high-k dielectric layer 284, Para [ 0041]) sequentially stacked on each of the first semiconductor channel layers (Fig 18, channel layers 215, Para [ 0033]), and a first gate electrode (Fig 18, metal layer 350, Para [ 0052]) on the first gate insulating layer (Fig 18, stack [279n, 280], Para [0011, 0050]), and
wherein the second transistor (Fig 18, transistor 200p) includes:
second semiconductor channel layers (channel layers 215, Para [ 0033]) spaced apart from each other and stacked on a second region of the substrate (substrate 202) in the vertical direction (Fig 18, substrate 202), a second gate insulating layer (Fig 18, stack [279P, 280], Para [0011, 0050]) surrounding the second semiconductor channel layers (Fig 18, channel layers 215, Para [ 0033]), and including a second interfacial insulating layer (interfacial layer 280, Para [ 0011]), a second lower high-k dielectric layer (high-k dielectric layer 282p, Para [ 0033]) containing the first metal element (high-k dielectric layer 282p, Para [ 0033]), a second composite dielectric layer (high-k dielectric layer 284, Para [ 0041]) containing the first metal element (high-k dielectric layer 284, Para [ 0041]) and the second metal element (high-k dielectric layer 284, Para [ 0041]), and a second upper high-k dielectric layer (high-k dielectric layer 286, Para [ 0049]) containing the second metal element (high-k dielectric layer 286, Para [ 0049]), the second interfacial insulating layer (interfacial layer 280, Para [ 0011]), the second lower high-x dielectric layer (high-k dielectric layer 282p, Para [ 0033]), the second composite dielectric layer (high-k dielectric layer 284, Para [ 0041]), and the second upper high-k dielectric layer (high-k dielectric layer 286, Para [ 0049]) sequentially stacked on each of the second semiconductor channel layers (channel layers 215, Para [ 0033]), and a second gate electrode (metal layer 350, Para [ 0052]) on the second gate insulating layer (stack [279P, 280], Para [0011, 0050]).
Regarding claim 4. Chang discloses the semiconductor device of claim 1, Chang further discloses wherein the first metal element includes at least one of hafnium (Hf) and zirconium (Zr), (Para [ 0012-0013]) and wherein each of the first lower high-x dielectric layer and the second lower high-x dielectric layer includes hafnium oxide or zirconium oxide (Para [ 0012-0013, 0033, 0041, 0049]).
Regarding claim 5. Chang discloses the semiconductor device of claim 1, Chang further discloses wherein the first lower high-k dielectric layer and the second lower high-k dielectric layer have the same thickness (Para [ 0014]).
Regarding claim 6. Chang discloses the semiconductor device of claim 5, Chang further discloses wherein the thickness of each of the first and second lower high-k dielectric layers is in a range of 5 A to 15 A (Para [ 0014]).
Regarding claim 7. Chang discloses the semiconductor device of claim 1, Chang further discloses wherein the second metal element includes at least one of aluminum (Al), hafnium (Hf), zirconium (Zr), and lanthanum (La), (Para [ 0012-0013, 0033, 0041, 0049]) and wherein the second upper high-x dielectric layer includes aluminum oxide, hafnium oxide, zirconium oxide, or lanthanum oxide (Para [ 0012-0013, 0033, 0041, 0049]).
Regarding claim 8. Chang discloses the semiconductor device of claim 1, Chang further discloses wherein each of the first composite dielectric layer (Para [ 0012-0013]) and the second composite dielectric layer includes the same oxide containing the first metal element and the second metal element (Para [ 0012-0013]).
Regarding claim 9. Chang discloses the semiconductor device of claim 8, Chang further discloses wherein the first metal element includes at least one of hafnium and zirconium, (Para [ 0012-0013]) and wherein the second metal element includes at least one of aluminum, hafnium, zirconium, and lanthanum (Para [ 0012-0013]).
Regarding claim 10. Chang discloses the semiconductor device of claim 1, Chang further discloses wherein each of the first and second composite dielectric layers has a thickness in a range of 2Aᵒ to 10 Aᵒ, (Para [ 0014]) and wherein the thickness of the second upper high-x dielectric layer is in a range of 5 Aᵒ to 15 Aᵒ (Para [ 0014]).
Regarding claim 11. Chang discloses the semiconductor device of claim 1, Chang further discloses wherein each of the first and second lower high-K dielectric layers includes hafnium oxide (Para [ 0012-0013, 0033, 0041, 0049]), wherein the second upper high-K dielectric layer includes aluminum oxide (Para [ 0012-0013, 0033, 0041, 0049]), and wherein each of the first and second composite dielectric layers includes an oxide containing hafnium and aluminum (Para [ 0012-0013, 0033, 0041, 0049]).
Regarding claim 12. Chang discloses the semiconductor device of claim 1, Chang further discloses wherein each of the first interfacial insulating layer and the second interfacial insulating layer includes the same dielectric material (Para [ 0012-0013, 0033, 0041, 0049]).
Regarding claim 13. Chang discloses the semiconductor device of claim 12, Chang further discloses wherein each of the first and second interfacial insulating layers includes silicon oxide or silicon oxynitride (Para [ 0011]).
Regarding claim 14. Chang discloses the semiconductor device of claim 12, Chang further discloses wherein each of the first interfacial insulating layer and the second interfacial insulating layer has the same thickness (Para [ 0033]).
Regarding claim 15. Chang discloses the semiconductor device of claim 14, Chang further discloses wherein the thickness of each of the first and second interfacial insulating layers is in a range of 5 Aᵒ to 10 Aᵒ (0.5 nm, Para [ 0033]).
Regarding claim 16. Chang discloses a semiconductor device (Fig 18 [A-C]) comprising:
a substrate (Fig 18 [A-C], substrate 202, Para [ 0035]) including an active pattern (lower channel layer 215, Para [ 0033]) extending in a first direction;
semiconductor channel layers (channel layers 215, Para [ 0033]) spaced apart from each other (channel layers 215, Para [ 0033]) and stacked on the active pattern (lower channel layer 215, Para [ 0033]) in a direction perpendicular to an upper surface of the substrate (Fig 18 [A-C], substrate 202);
a gate structure (gate stack 240n, Para [0011, 0050]) on the substrate (Fig 18 [A-C], substrate 202), extending in a second direction, intersecting the semiconductor channel layers (channel layers 215, Para [ 0033]), and respectively surrounding the semiconductor channel layers (channel layers 215, Para [ 0033]); and
a source/drain region (S/D features 260, Para [ 0052]) disposed on the active pattern (lower channel layer 215, Para [ 0033]) on at least one side of the gate structure (gate stack 240n, Para [0011, 0050]) and respectively connected to the semiconductor channel layers (channel layers 215, Para [ 0033]), wherein the gate structure (gate stack 240n, Para [0011, 0050]) respectively surrounds the semiconductor channel layers (channel layers 215, Para [ 0033]) and includes a gate insulating layer (stack [279n, 280], Para [0011, 0050]) and a gate electrode (metal layer 350, Para [ 0052]) disposed on the gate insulating layer (stack [279n, 280], Para [0011, 0050]), and wherein the gate insulating layer (stack [279n, 280], Para [0011, 0050]) includes an interfacial insulating layer (interfacial layer 280, Para [ 0011]), a lower high-k dielectric layer containing a first metal element (high-k dielectric layer 282p, Para [0012-0013, 0033]), a composite dielectric layer containing the first metal element (high-k dielectric layer 284, Para [0012-0013, 0041]) and a second metal element different from the first metal element (high-k dielectric layer 284, Para [ 0012-0013, 0041]), and an upper high-x dielectric layer (high-k dielectric layer 286, Para [ 0012-0013, 0049]) containing the second metal element (high-k dielectric layer 286, Para [0012-0013, 0049]), sequentially disposed on each of the semiconductor channel layers (channel layers 215, Para [ 0033]).
Regarding claim 18. Chang discloses the semiconductor device of claim 16, Chang further discloses wherein the first metal element includes at least one of hafnium and zirconium (Para [ 0012-0013, 0033, 0041, 0049]), and wherein the second metal element includes at least one of aluminum, hafnium, zirconium, and lanthanum (Para [ 0012-0013, 0033, 0041, 0049]).
Regarding claim 19. Chang discloses the semiconductor device of claim 18, Chang further discloses wherein: the interfacial insulating layer includes silicon oxide or silicon oxynitride (Para [ 0011-0013]), the lower high-K dielectric layer includes hafnium oxide, the composite dielectric layer includes an oxide containing hafnium and aluminum, and the upper high-K dielectric layer includes aluminum oxide (Para [ 0012-0013, 0033, 0041, 0049]).
Regarding claim 20. Chang discloses a semiconductor device (Fig 18 [A-C]) comprising:
a substrate (Fig 18 [A-C], substrate 202, Para [ 0035]) including a first region (200N, Para [ 0011]) and a second region (200P, Para [ 0011]);
a first active pattern (lower channel layer 215, Para [ 0033]) on the first region (200N, Para [ 0011]) of the substrate (Fig 18 [A-C], substrate 202, Para [ 0035]);
a first gate insulating layer (stack [279n, 280], Para [0011, 0050]) including a first interfacial insulating film (interfacial layer 280, Para [ 0011]), a first lower high-K dielectric film (high-k dielectric layer 282, Para [ 0033]), and a first composite dielectric film (high-k dielectric layer 284, Para [ 0041]), sequentially stacked on the first active pattern (lower channel layer 215, Para [ 0033]);
a first gate electrode (metal layer 350, Para [ 0052]) on the first gate insulating layer (stack [279n, 280], Para [0011, 0050]);
a second active pattern (lower channel layer 215, Para [ 0033]) on the second region (200P, Para [ 0011]) of the substrate (Fig 18 [A-C], substrate 202); and
a second gate insulating layer (stack [279P, 280], Para [0011, 0050]) including a second interfacial insulating film (interfacial layer 280, Para [ 0011]), a second lower high-K dielectric film (high-k dielectric layer 282p, Para [ 0033]), a second composite dielectric film (high-k dielectric layer 284, Para [ 0041]), and a second upper high-K dielectric film (high-k dielectric layer 286, Para [ 0049]), sequentially stacked on the second active pattern (lower channel layer 215, Para [ 0033]), wherein:
each of the first and the second lower high-k dielectric films includes a first metal element (Para [ 0012-0013, 0033, 0041, 0049]), the second upper high-k dielectric film includes a second metal element (Para [ 0012-0013, 0033, 0041, 0049]), and each of the first and the second composite dielectric films includes both of the first and the second metal elements (Para [ 0012-0013, 0033, 0041, 0049]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US 2021/0399104 A1; hereafter Chang).
Regarding claim 2. Chang discloses the semiconductor device of claim 1, But Chang does not disclose explicitly wherein the second gate insulating layer has a thickness greater than that of the first gate insulating layer.
However, Chang discloses interfacial layer 280 has a thickness of about 0.5 nm to about 1.5 nm (Para [ 0033]) and each of the layers 282, 282p, 284, 284n, and 286 has a thickness in a range of about 2 Å to 15 Å in some embodiments. So, the total thickness of each triple layer stack 279n and 279p is about 6 Å to 45 Å (Para [ 0014]). Therefore, based on the range of the thickness, second gate insulating layer can be greater thickness than that of the first gate insulating layer.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to Modify Chang teaching to have desired thickness in the second gate insulating layer for further advantage such as to provide controlled threshold voltage in the gate structure.
In addition, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to vary thickness, through routine experimentation, the result-effective variable of gate insulating layer thickness (result-effective at least insofar as the thickness affects the size of the device) in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed gate insulating layer thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Regarding claim 3. Chang discloses the semiconductor device of claim 2, But Chang does not disclose explicitly wherein the thickness of the second gate insulating layer is 40 Aᵒ or less.
However, Chang discloses interfacial layer 280 has a thickness of about 0.5 nm to about 1.5 nm (Para [ 0033]) and each of the layers 282, 282p, 284, 284n, and 286 has a thickness in a range of about 2 Å to 15 Å in some embodiments. So, the total thickness of each triple layer stack 279n and 279p is about 6 Å to 45 Å (Para [ 0014]). Therefore, based on the range of the thickness, the thickness of the second gate insulating layer can be 40 Aᵒ or less.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to Modify Chang teaching to have desired thickness of the second gate insulating layer for further advantage such as to provide controlled threshold voltage in the gate structure.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). >See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Regarding claim 17. The semiconductor device of claim 16, But Chang does not disclose explicitly wherein the gate insulating layer has a thickness of 40 Aᵒ or less.
However, Chang discloses wherein the gate insulating layer has a thickness of 40 Aᵒ or less (Para [ 0014]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). >See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to Modify Chang teaching to have desired thickness of the second gate insulating layer for further advantage such as to provide controlled threshold voltage in the gate structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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