Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 12/20/23. Claims 1-20 are pending in this application.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. §102 as being unpatentable over Mazza (US 20240222356 A1), filed 2023-01-03.
Regarding claim 1, Mazza discloses a semiconductor device comprising: a plurality of cells (see 116 disclosing active region)comprising a 1st cell (see fig 13 116 contains cells, see para [0042]); and a 1st backside power rail and a 2nd backside power rail disposed below the 1st cell (see 160 and 1622 below 116 ), extended in a 1st direction (horizontally across the page in fig 13)and arranged in a 2nd direction intersecting the 1st direction (arranged vertically across the page), wherein the 1st backside power has a 1st width, and the 2nd backside power rail has a 2nd width which is different from the 1st width (see fig 13, disclosing 160 and 162e are different widths). See fig 13 reproduced below:
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Regarding claim 2, Mazza discloses the semiconductor device of claim 1, wherein the 1st backside power rail is disposed below an upper cell boundary or a lower cell boundary of the 1st cell, and the 2nd backside power rail is disposed below an inside region of the 1st cell(see fig 13, where cells 116 is disposed between power rails 160/162).
Regarding claim 3, Mazza discloses the semiconductor device of claim 2, further comprising a 3rd backside power rail, wherein the 1st and 3rd backside power rails are disposed below the upper and lower cell boundaries of the 1st cell, respectively(see fig 13, where cells 116 is disposed between power rails 160/162).
Regarding claim 4, Mazza discloses the semiconductor device of claim 3, wherein the 1st and 3rd backside power rails are configured to provide the 1st cell with a 1st voltage, and the 2nd backside power rail is configured to provide the 1st cell with a 2nd voltage different from the 1st voltage(see para [0058] disclosing voltage drops).
Regarding claim 5, Mazza discloses the semiconductor device of claim 3, wherein the 3rd backside power rail has a3rd width which is the same as the 1st width (see fig 13, disclosing 162I having same widths).
Regarding claim 6, Mazza discloses the semiconductor device of claim 1, wherein the plurality of cells comprises a 2nd cell having a same cell height as the 1st cell. wherein a 3rd backside power rail is arranged in the 1st direction and disposed below the 2nd cell(see fig 13, where cells 116 is disposed between power rails 160/162), and wherein the 3rd backside power rail has a 3rd width which is the same as the 1st width(see fig 13, disclosing 162I having same widths).
Regarding claim 7, Mazza discloses the semiconductor device of claim 1, wherein the 1st cell comprises a logic circuit configured to perform a logic function (see para [0042] disclosing logic).
Regarding claim 8, Mazza discloses the semiconductor device of claim 7, further comprising a dummy cell which does not comprise any logic circuit configured to perform a logic function(see para [0042] disclosing active regions, disclosing spacing between devices, hence unused active areas).
Regarding claim 9, Mazza discloses the semiconductor device of claim 8, wherein the 1st cell and the dummy cell are disposed in different rows extended in the 1st direction in a lay out of the semiconductor device (see para [0042] disclosing dummy areas adjacent to device areas).
Regarding claim 10, Mazza discloses the semiconductor device of claim 7, further comprising a 3rd backside power rail having a 3rd width which is the same as the 1st width(see fig 13, disclosing 162I having same widths), wherein the 1st and 3rd power rails are disposed below the upper and lower cell boundaries of the 1st cell, respectively(see fig 13, where cells 116 is disposed between power rails 160/162), and configured to provide the 1st cell with a 1st voltage, and wherein the 2nd backside power rail is disposed below an inside region of the 1st cell, and configured to provide the 1st cell with a 2nd voltage different from the 1st voltage(see para [0058] disclosing voltage drops).
Regarding claim 11, Mazza discloses a semiconductor device comprising: a plurality of cells comprising 1st cells arranged in a 1st row of a layout of the semiconductor device(see fig 13 116 contains cells, see para [0042]); and a 1st backside power rail and a 2nd backside power rail disposed below the 1st cells(see 160 and 1622 below 116 ), extended in a 1st direction (see fig 13, extending horizontally across the page), and arranged in a 2nd direction intersecting the 1st direction (see fig 13, extending vertically along the page), wherein the 1st backside power has a 1st width, and the 2nd backside power rail has a 2nd width which is different from the 1st width(see fig 13, disclosing 160 and 162e are different widths). See fig 13 reproduced below:
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Regarding claim 12, Mazza discloses the semiconductor device of claim 11, wherein the 1st backside power rail is disposed below upper cell boundaries or lower cell boundaries of the 1st cells, and the 2nd backside power rail is disposed below an inside region of each of the 1st cells (see fig 13, where cells 116 is disposed between power rails 160/162).
Regarding claim 13, Mazza discloses the semiconductor device of claim 12, further comprising a 3rd backside power rail, wherein the 1st and 3rd backside power rails are disposed below the upper boundaries and the lower cell boundaries of the 1st cells, respectively(see fig 13, where cells 116 is disposed between power rails 160/162).
Regarding claim 14, Mazza discloses the semiconductor device of claim 13, wherein the 1st and 3rd backside power rails are configured to provide the 1st cell with a 1st voltage, and the 2nd backside power rail is configured to provide the 1st cell with a 2nd voltage different from the 1st voltage (see para [0058] disclosing voltage drops).
Regarding claim 15, Mazza discloses the semiconductor device of claim 3, wherein the 3rd backside power rail has a3rd width which is the same as the 1st width (see fig 13, 162i).
Regarding claim 16, Mazza discloses the semiconductor device of claim 11, wherein the plurality of cells comprises 2nd cells arranged in a 2nd row of the layout of the semiconductor device, wherein a 3rd backside power rail is arranged in the 1st direction and disposed below the 2nd cells, and wherein the 3rd backside power rail has a 3rd width which is the same as the 1st width (see fig 16 where active region 116 is between 160, 162e and 162i’s has the same width).
Regarding claim 17, Mazza discloses the semiconductor device of claim 11, wherein the 1st cells comprise: a logic cell comprising a logic circuit configured to perform a logic function(see fig 13 116 contains cells, see para [0042]); and a dummy cell which does not comprise any logic circuit configured to perform a logic function(see para [0042] disclosing active regions, disclosing spacing between devices, hence unused active areas).
Regarding claim 18, Mazza discloses a semiconductor device comprising: a plurality of cells in a cell architecture comprising: at least one 1st cell comprising a logic circuit configured to perform a logic function (see fig 13 116 contains cells, see para [0042]), and at least one dummy cell which does not comprise any logic circuit configured to perform a logic function (see para [0042] disclosing active regions, disclosing spacing between devices, hence unused active areas); and a plurality of backside power rails disposed below the plurality of cells, and extended in a1st direction in parallel with each other (see fig 13, disclosing 160 and 162e).
Regarding claim 19, Mazza discloses the semiconductor device of claim 18, wherein the at least one dummy cell comprises a plurality of gate structures (see para [0042] disclosing multiple gate structures).
Regarding claim 20, Mazza discloses the semiconductor device of claim 18, wherein the plurality of backside power rails have different widths (see fig 13, disclosing 160 and 162e are different widths). See fig 13 reproduced below:
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/ Primary Examiner, Art Unit 2893