Prosecution Insights
Last updated: July 05, 2026
Application No. 18/382,368

MICROFABRICATED ULTRASONIC TRANSDUCERS AND RELATED APPARATUS AND METHODS

Non-Final OA §103
Filed
Oct 20, 2023
Priority
Jul 14, 2014 — provisional 62/024,179 +7 more
Examiner
KIM, SU C
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BFLY Operations Inc.
OA Round
3 (Non-Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
65%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
705 granted / 910 resolved
+9.5% vs TC avg
Minimal -12% lift
Without
With
+-12.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
32 currently pending
Career history
955
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
82.0%
+42.0% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
1.7%
-38.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 910 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/11/2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kupnik et al. (US 20090122651) in view of Regarding claim 1, Kupnik discloses that an ultrasound device, comprising: ultrasonic transducer cavities 110 (Fig. 1(a-c); a membrane 118, positioned above the ultrasonic transducer cavities 110, comprising a silicon layer (para. 0086, note: “- - doped silicon - - silicon nitride doped silicon carbide, doped polycrystalline silicon - -“) that seals the ultrasonic transducer cavities (Fig. 1 (a-c)); electrode regions 120, 130, 138, positioned below the ultrasonic transducer cavities 110, configured to control vibration of the membrane (a function of membrane); and an electronic unit substrate 136, positioned below the electrode regions 120, 130, 138. Kupnik fails to specify that an electronic unit substrate can be a complementary metal-oxide-semiconductor (CMOS) substrate. However, Lin suggest that an electronic unit substrate can be a complementary metal-oxide-semiconductor (CMOS) 114 substrate (Fig. 1, Para. 0013 & 0029). Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Kupnik with an electronic unit substrate can be a complementary metal-oxide-semiconductor (CMOS) substrate as taught by Lin in order to enhance variety of the transistors or variety of controlling elements (para. 0013) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art. Reclaim 2, Kupnik & Lin disclose that isolation regions 108 disposed between the electrode regions 120, 130, 138 of adjacent ultrasound transducer cavities 110 when viewed in the vertical direction, wherein the isolation regions are doped (Kupnik, para. 0106). Reclaim 3, Kupnik & Lin disclose that an embedded electrical contact between the CMOS substrate 136 and an engineered substrate 101 that includes the ultrasonic transducer cavities 110, wherein ends of the embedded electrical contact 124 directly connect: a bond point between the CMOS substrate 136 and the engineered substrate 101; and an electrical contact disposed on the membrane (Kupnik, Fig. 1 (b-c)). Reclaim 4, Kupnik & Lin disclose that the embedded electrical contact 124 protrudes though the engineered substrate 101 along the vertical direction (Kupnik, Fig. 1(b-c)). Reclaim 5, Kupnik & Lin disclose that the embedded electrical contact protrudes though the membrane along the vertical direction (Kupnik, Fig. 1(b-c)). Response to Arguments Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SU C KIM/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Oct 20, 2023
Application Filed
Aug 12, 2024
Non-Final Rejection mailed — §103
Feb 12, 2025
Response Filed
May 05, 2025
Final Rejection mailed — §103
Jan 05, 2026
Response after Non-Final Action
Feb 11, 2026
Request for Continued Examination
Feb 23, 2026
Response after Non-Final Action
Mar 30, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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SEMICONDUCTOR DEVICE WITH RECESSED GATE AND METHOD FOR FABRICATING THE SAME
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
65%
With Interview (-12.1%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 910 resolved cases by this examiner. Grant probability derived from career allowance rate.

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