Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species 3 of figures 9-11 in the reply filed on 02/13/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 4-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al., U.S. Patent 11,424,185.
Chang et al. shows the invention as claimed including a semiconductor device comprising:
An active pattern extending in a first direction;
A gate structure (15,12,30) which is placed on the active pattern to be spaced apart from each other in the first direction, and includes a gate electrode 15 and a gate spacer 12, the gate electrode extending in a second direction intersecting the first direction;
A gate contact 102 on the gate structure 15;
A source/drain pattern 50 on the active pattern;
A source/drain contact 70 on the source/drain pattern; and
A via plug 100 on the source/drain contact 70, wherein an upper surface of the gate contact and an upper surface of the via plug are placed on the same plane (see figs. 1C-1D and col. 3-line 12 to col. 4-line 33), and wherein a lower surface of the gate contact and a lower surface of the via plug are different in height, on the basis of an upper surface of the active pattern (see figs. 1A-1D and col. 2-line 53 to col. 4-line 42).
Regarding dependent claim 4, note that in Chang et al. the gate contact 102 includes ruthenium or a ruthenium alloy and therefore does not include titanium.
Furthermore, concerning dependent claim 5, note that the gate contact does also not include Si-H bonds since there is no silicon in the gate contact 102.
As to dependent claim 6, the gate contact does also not include boron.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., U.S. Patent 11,424,185 in view of Adusumilli et al., U.S. Patent 9,837,357.
Chang et al. is applied as above but does not expressly disclose where the gate contact is a single grain. Howver, Adusumilli et al. discloses forming single grain contacts in CMOS based devices (see col. 4-lines 16-23). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Chang et al. so as to form the gate contact of a single grain because Adusumilli et al. discloses the use of single grain contacts in order to lower contact resistance.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., U.S. Patent 11,424,185 in view of Liaw, US 2016/0276331.
Chang et al. is applied as above but does not expressly disclose wherein each of the via plug and the gate contact includes tungsten. Liaw discloses where a via plug and gate contact can both comprise tungsten (see, for example, paragraphs 0068). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Chang et al. so as to comprise a via plug and gate contact of tungsten as suggested by Liaw because this shows that tungsten is a suitable material for via plugs and gate contacts.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., U.S. Patent 11,424,185.
Chang et al. is applied as above but does not expressly disclose a contact silicide film between between the source/drain pattern and the source/drain contact. However, the examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form the claimed silicide film because in such a way the resistance between the silicon substrate and overlying metal layers can be reduced.
Claim(s) 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., U.S. Patent 11,424,185 in view of Lee et al., US 2021/0257474.
Chang et al. is applied as above but does not expressly disclose wherein the gate contact includes: a contact liner, and a contact filling film on the contact liner, and wherein the contact liner and the contact filling film include the same material. Lee et al. discloses wherein the gate contact includes: a contact liner 180a, and a contact filling film 180b on the contact liner, and wherein the contact liner and the contact filling film can include the same material, for example, cobalt (see paragraphs 0100, for example). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Chang et al. so as to comprise the claimed gate contact configuration of Lee et al. because Lee et al. shows this to be a suitable gate contact configuration in a semiconductor device.
Regarding dependent claim 9, note that Lee et al. discloses wherein a lower surface of the contact filling film has a convex shape toward the gate electrode (see fig. 2).
As to dependent claim 10, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to determine through routine experimentation the optimum thickness of the contact liner depending upon a variety of factors including the particular dimension of the device features and would not lend patentability to the instant application absent a showing of unexpected results.
With respect to dependent claim 11, Chang et al. is applied as above but does not expressly disclose a via liner, and a via filling film on the via liner, and wherein the via liner and the via filling film include tungsten. Lee et al. discloses a via liner 210a, and a via filling film 210b on the via liner, and wherein the via liner and the via filling film include tungsten (see paragraphs 0117-0118). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Chang et al. so as to comprise the claimed via plug of Lee et al. because Lee et al. shows such a via plug to be a suitable configuration for a semiconductor device.
As to dependent claim 12, Chang et al. and Lee et al. disclose wherein a lower surface of the via filling film has a convex shape toward the source/drain contact. However, a prima facie case of obviousness exists because the particular shape of the via plug is a matter of choice which a person of ordinary skill in the art would have found obvious absent any new or unexpected result.
Claim(s) 13 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., U.S. Patent 11,424,185 in view of Liaw, US 2016/0276331 and further in view of Adusumilli et al., U.S. Patent 9,837,357.
Chang et al. shows the invention substantially as claimed including an active pattern extending in a first direction;
A gate structure (15,12,30) which is placed on the active pattern to be spaced apart from each other in the first direction, and includes a gate electrode 15 and a gate spacer 12, the gate electrode extending in a second direction intersecting the first direction;
A gate contact 102 on the gate structure 15;
A source/drain pattern 50 on the active pattern;
A source/drain contact 70 on the source/drain pattern; and
A via plug 100 on the source/drain contact 70 (see figs. 1A-1D and col. 2-line 53 to col. 4-line 42).
Chang et al. does not expressly disclose wherein each of the gate contact and the via plug does not include titanium, and includes tungsten of a single grain.
Liaw discloses where a via plug and gate contact can both comprise tungsten (see, for example, paragraphs 0068). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Chang et al. so as to comprise a via plug and gate contact of tungsten as suggested by Liaw because this shows that tungsten is a suitable material for via plugs and gate contacts. Regarding the tungsten being single grain, Adusumilli et al. discloses forming single grain contacts in CMOS based devices (see col. 4-lines 16-23). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Chang et al. modified by Liaw so as to form the gate contact and via plug of a single grain because Adusumilli et al. discloses the use of single grain contacts in order to lower contact resistance.
As to dependent claim 17 note that as also described in the rejection of claim 1 an upper surface of the gate contact and an upper surface of the via plug in the invention of Chang et al. are placed on the same plane.
With respect to dependent claim 18, the examiner takes official notice that the active pattern is prima facie obvious and notoriously well known in the art because the configuration that includes the plurality of active patterns because in such a way a highly integrated device can be fabricated.
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., U.S. Patent 11,424,185 in view of Liaw, US 2016/0276331 and further in view of Adusumilli et al., U.S. Patent 9,837,357 as applied to claims 13 and 17-18 above, and further in view of Lee et al., US 2021/0257474.
Chang et al., Liaw, and Adusumili et al. are applied as above but do not expressly disclose where the contact liner, contact filling film, via liner, and via filling film include tungsten. Lee et al. discloses wherein the gate contact includes: a contact liner 180a, and a contact filling film 180b on the contact liner, and wherein the contact liner and the contact filling film can include the same material (see paragraphs 0100, for example). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Chang et al. so as to comprise the claimed gate contact configuration of Lee et al. because Lee et al. shows this to be a suitable gate contact configuration in a semiconductor device. Additionally, Lee et al. discloses a via liner 210a, and a via filling film 210b on the via liner, and wherein the via liner and the via filling film include tungsten (see paragraphs 0117-0118). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Chang et al. so as to comprise the claimed via plug of Lee et al. because Lee et al. shows such a via plug to be a suitable configuration for a semiconductor device.
Concerning dependent claim 15, note that in Lee et al. an upper surface of the bottom portion has a convex shape toward the gate electrode (see, for example, fig. 2 of Lee et al.).
Regarding dependent claim 16 and the via liner configuration, a prima facie case of obviousness exists because the particular shape of the via plug is a matter of choice which a person of ordinary skill in the art would have found obvious absent any new or unexpected result.
Allowable Subject Matter
Claims 19-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, particularly Chang et al., U.S. Patent 11,424,185, either singly or in combination, fails to anticipate or render obvious, the following limitations in combination with the claimed limitations: a wiring line which is in contact with the gate contact and the via plug, wherein: an upper surface of the gate contact and an upper surface of the via plug are placed on the same plane, the gate contact and the via plug each includes tungsten of single grain, the gate contact includes a contact liner, and a contact filling film on the contact liner, and a lower surface of the contact filling film has a convex shape toward the gate electrode, as required by independent claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2024/0105773 discloses a memory device with a via plug and gate contact configuration.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
May 30, 2026
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