DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Invention I, Species III (claims 1-8, and 10-12) in the reply filed on 3/24/26 is acknowledged. Claims 9, and 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/24/26. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “802” has been used to designate both dashed line and hybrid bonded memory stacks. See, for example, paragraph [ 0086] and [0090]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, (1) a second layer of memory devices is located between the first layer of memory devices and a back-end-of-the-line (BEOL) interconnect structure (claim 5) , and metal lines with a largest pitch is located in the middle of the BEOL interconnect structure (claim 7) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 2, 3, 5 thru 8, and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In lines 1-2 of claim 2, the applicant states “wherein a first layer of memory devices and a second layer of memory devices … are the same.”; however, it is unclear what feature (i.e. structure, feature, position, function, etc.) of the first layer and second layer is “the same.” Appropriate clarification and/or correction are required. In lines 1-2 of claim 3, the applicant states “wherein a first layer of memory devices and a second layer of memory devices … are different.”; however, it is unclear what feature of the first layer and second layer is “different.” Appropriate clarification and/or correction are required. In line s 4-5 of claim 5 , the applicant states the limitation “ a second layer of memory devices is located between the first layer of memory devices and a back-end-of-the-line (BEOL) interconnect structure;” ; however, it appears (see, for example, FIG. 10, and 8) that the second layer of memory devices 220 is located between the first layer of memory devices 1 2 0 and backside interconnect structure 630 , rather than the back-end-of-the-line (BEOL) interconnect structure 530 . In FIG. 10, the applicant shows the back-end-of-the-line (BEOL) interconnect structure 530 being between first layer of memory devices 120 and the second layer of memory devices 220, and still having the first layer of memory devices 120 being located below a semiconductor substrate 710B as disclosed in line 3 of claim 5 . Appropriate clarification and/or correction are required. In claim 7, the applicant states “metal lines with a largest pitch is located in the middle of the BEOL interconnect structure.”; however, it is unclear how the applicant is defining the term “pitch.” Pitch is usually defined in the art as the distance between structures; however, in paragraph [0058] of the specification, the applicant states “gate length or gate pitch” as if gate pitch is also the gate length. Also, in FIG. 4, the applicant shows metal lines 236/136 which have the largest length in the middle 402 of the BEOL interconnect structure 230/130, and the metal lines 236/136 are only on the middle of the BEOL interconnect structure 230/130 , and therefore, would be the only location wherein the metal lines have a pitch , and therefore, a “largest” pitch . Appropriate clarification and/or correction are required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. C laim(s) 1 , and 4 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Sukekawa US 2019/0363074 A1 . Sukekawa discloses (see, for example, FIG. 8) a memory device comprising a stack of memory dice 10A/10B wherein each memory die in the stack of memory dies includes two or more layers of memory devices Memory Cell Array , which are layers of memory cell arrays, i.e. memory cell devices. In paragraph [0030], Sukekawa discloses the memory chips 10A and 10B. Regarding claim 4, see, for example, FIG. 8 wherein Sukekawa discloses a first memory die 10A comprising a first BEOL interconnect structure BE4 being hybrid bonded to a second BEOL interconnect structure BE1 of a second memory die 10B. Further, the limitation (i.e. formed by hybrid bonding) is a product-by process limitation that relate s to the process of making a memory device, and not to the final structure of the memory device. A ny language that does not contribute to the device’s final structure is given no patentable weight as the claims are directed towards device, not the process of making. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. In view of the 112 rejection above, c laim (s) 2, and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sukekawa US 2019/0363074 A1 as applied to claim 1, and 4 above. Sukekawa does specifically disclose a first layer of memory devices and a second layer of memory devices in each memory die in the stack of memory dies being the same or different . However, it was well known in the art to have a first layer and/or second layer of memory device having same or different structure s , feature s , position s , function s, etc. according the preferences of the user as a matter of obvious design choice It would have been obvious to one of ordinary skill in the art , at a time prior to the effective filing date, to have a first layer of memory devices and a second layer of memory devices in each memory die in the stack of memory dies being the same or different in order to produce memory dies that p erform tasks having storage, speed, scalability, etc . requirements according to the preferences of the use r as a matter of obvious design choice . Also see the 112 rejection above. Regarding claim 3, see the rejection for claim 2 above. In view of the 112 rejection, c laim (s) 5 thru 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sukekawa US 2019/0363074 A1 as applied to claim 1, and 4 above, and further in view of Gomes et al. US 2021/0125990 A1. Sukekawa does specifically disclose each memory die in the stack of memory dies: a first layer of memory devices being located below a semiconductor substrate; a second layer of memory devices being located between the first layer of memory devices and a back-end-of-the-line (BEOL) interconnect structure; and a backside interconnect structure being located below the second layer of memory devices. However, Gomes discloses (see, for example, FIG. 5H) a memory device 516 comprising memory dies 540-2/540-1 wherein each memory die includes multiple memory layers 528, substrates 52 6 , BEOL interconnect structure 520-2, and backside interconnect structure 538. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to include each memory die in the stack of memory dies: a first layer of memory devices is located below a semiconductor substrate; a second layer of memory devices is located between the first layer of memory devices and a back-end-of-the-line (BEOL) interconnect structure; and a backside interconnect structure being located below the second layer of memory devices in order to provide a support structure that increases the density of memory cells while reducing the footprint area. Also, see 112 rejection above. Regarding claim 6, see, for example, FIG. 5H wherein Gomes discloses a BEOL interconnect structure 520-2. Further, the limitation (i.e. formed by hybrid bonding) is a product-by process limitation that relat es to the process of making a memory device, and not to the final structure of the memory device. Any language that does not contribute to the device’s final structure is given no patentable weight as the claims are directed towards device, not the process of making. Regarding claim 7, see, for example, FIG. 5H wherein Gomes discloses a metal lines 524, which have the largest pitch being located in the middle of the BEOL interconnect structure 520-2. C laim (s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sukekawa US 2019/0363074 A1 in view of Gomes et al. US 2021/0125990 A1 as applied to claim s 5-7 above, and further in view of Chen et al. US 2024/0379623 A1. Sukekawa in view of Gomes does specifically disclose each memory die further includes one or more through-silicon-vias (TSVs), the one or more TSVs formed within, and extending through, the semiconductor substrate, the first layer of memory devices, the BEOL interconnect structure, the second layer of memory devices, and the backside interconnect structure . However, Chen discloses (see, for example, FIG. 3A) a memory device comprising through-silicon-vias 400 extending through multiple semiconductor structures 200. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to include one or more through-silicon-vias (TSVs), the one or more TSVs formed within, and extending through, the semiconductor substrate, the first layer of memory devices, the BEOL interconnect structure, the second layer of memory devices, and the backside interconnect structure in order to connect multiple dies together with a compact, easy-to-form structure . C laim (s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sukekawa US 2019/0363074 A1 in view of Gomes et al. US 2021/0125990 A1 as applied to claims 5-7 above , and further in view of Chen et al. US 2020/0091063 A1 . Sukekawa in view of Gomes does specifically disclose each memory die in the stack of memory dies further includes one or more deep trench capacitors formed within the semiconductor subst r ate. However, Chen discloses (see, for example, FIG. 1D- 1 E ) a device comprising a deep trench capacitor 150 formed within a semiconductor substrate 110B’. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to include one or more deep trench capacitors formed within the semiconductor subst r ate for power decoupling , and reduc ing noise and leakage current within the memory device. C laim (s) 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sukekawa US 2019/0363074 A1 as applied to claim 1, and 4 above, and further in view of Ken et al. US 2013/0091315 A1. Sukekawa does specifically disclose the stack of memory dies being vertically stacked on top of a logic die. However, Ken discloses (see, for example, FIG. 5) a memory device 100 comprising a stack of memory dies 102/104 being vertically stacked on top of a logic die 106. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the stack of memory dies being vertically stacked on top of a logic die in order to control the memory arrays with improve d density and smaller packaging footprint. Regarding claim 12, Sukekawa does not disclose the logic die being connected to at least one of a n interposer or a package substrate; however, Ken discloses a memory device comprising a stack of memory dies 102/104, logic die 106, and substrate 114. It would have been obvious to one of ordinary skill in the art , at a time prior to the effective filing date, to have a substrate in order to support the entire memory device, and make further connections therein according to the preferences of the user. INFORMATION ON HOW TO CONTACT THE USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT EUGENE LEE whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1733 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 730-330 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT JOSHUA BENITEZ can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-270-1435 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Eugene Lee March 31, 2026 /EUGENE LEE/ Primary Examiner, Art Unit 2815