DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 thru 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee US 2013/0021866 A1. Lee discloses (see, for example, FIG. 18A) a memory device 180, comprising: a stack of memory dies 10, wherein each memory die 10 in the stack of memory dies includes: a first layer of memory devices 12; a second layer of memory devices 14 located above the first layer of memory devices; and a back-end-of-the-line (BEOL) interconnect structure 211t-213t located between the first and second layers of memory devices. Regarding the limitation “a stack of memory dies”, see, for example, paragraph [0233] wherein Lee discloses a plurality of the memory devices 10 may be connected to the memory controller 182.
Regarding claim 2, see, for example, FIG. 18A wherein Lee discloses the first layer of
memory devices 12 being structurally similar to the second layer of memory devices 14.
Regarding claim 3, see, for example, FIG. 18A wherein Lee discloses the first layer of
memory devices 12 being structurally different (i.e. the interconnect structure 211t-211t and data output pad DQ) to the second layer of memory devices 14.
Claim(s) 1, 3, 5, and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu US 2023/0422528 A1. Hu discloses (see, for example, FIG. 13) a memory device, comprising: a stack of memory dies 200/100, wherein each memory die 200/100 in the stack of memory dies includes: a first layer of memory devices 20; a second layer of memory devices 10 located above the first layer of memory devices 20; and a back-end-of-the-line (BEOL) interconnect structure 33 located between the first and second layers of memory devices.
Regarding claim 3, see, for example, FIG. 13 wherein Hu discloses the first layer of
memory devices 20 being structurally different to the second layer of memory devices 10.
Regarding claim 5, see, for example, FIG. 13 wherein Hu discloses the first layer of memory devices 20 is located on top of a semiconductor substrate 21; the second layer of memory devices 10 is on top of the BEOL interconnect structure 33; and a backside interconnect structure 40 is located on top of the second layer of memory devices.
Regarding claim 7, see, for example, FIG. 13 wherein Hu discloses a metal layer of the BEOL interconnect structure 33 having metal lines with a greatest thickness is located in a middle of the BEOL interconnect structure 33.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2013/0021866 A1 as applied to claim 1-3 above, and further in view of Gomes et al. US 2021/0125990 A1. Lee does specifically disclose for each memory die in the stack of memory dies: the first layer of memory devices is located on top of a semiconductor substrate; the second layer of memory devices is on top of the BEOL interconnect structure; and a backside interconnect structure is located on top of the second layer of memory devices. However, Gomes discloses (see, for example, FIG. 5H) a memory device 516 comprising memory dies 540-2/540-1 wherein each memory die includes multiple memory layers 528, substrates 520, BEOL interconnect structure 520-2, and backside interconnect structure 538. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the first layer of memory devices is located on top of a semiconductor substrate; the second layer of memory devices is on top of the BEOL interconnect structure; and a backside interconnect structure is located on top of the second layer of memory devices in order to provide a support structure that increases the density of memory cells while reducing the footprint area.
Regarding claim 7, see, for example, FIG. 5H wherein Gomes discloses a metal lines 524, which have the greatest thickness being located in the middle of the BEOL interconnect structure 520-2.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2013/0021866 A1 in view of Gomes et al. US 2021/0125990 A1 as applied to claims 5, and 7 above, and further in view of Chen et al. US 2024/0379623 A1. Lee in view of Gomes does specifically disclose each memory die further includes one or more through-silicon-vias (TSVs), the one or more TSVs formed within, and extending through, the semiconductor substrate, the first layer of memory devices, the BEOL interconnect structure, the second layer of memory devices, and the backside interconnect structure. However, Chen discloses (see, for example, FIG. 3A) a memory device comprising through-silicon-vias 400 extending through multiple semiconductor structures 200. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to include one or more through-silicon-vias (TSVs), the one or more TSVs formed within, and extending through, the semiconductor substrate, the first layer of memory devices, the BEOL interconnect structure, the second layer of memory devices, and the backside interconnect structure in order to connect multiple dies together with a compact, easy-to-form structure.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu US 2023/0422528 A1 as applied to claims 1, 3, 5, and 7 above, and further in view of Chen et al. US 2024/0379623 A1. Hu does specifically disclose each memory die further includes one or more through-silicon-vias (TSVs), the one or more TSVs formed within, and extending through, the semiconductor substrate, the first layer of memory devices, the BEOL interconnect structure, the second layer of memory devices, and the backside interconnect structure. However, Chen discloses (see, for example, FIG. 3A) a memory device comprising through-silicon-vias 400 extending through multiple semiconductor structures 200. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to include one or more through-silicon-vias (TSVs), the one or more TSVs formed within, and extending through, the semiconductor substrate, the first layer of memory devices, the BEOL interconnect structure, the second layer of memory devices, and the backside interconnect structure in order to connect multiple dies together with a compact, easy-to-form structure.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2013/0021866 A1 in view of Gomes et al. US 2021/0125990 A1 as applied to claims 5, and 7 above, and further in view of Chen et al. US 2020/0091063 A1. Lee in view of Gomes does specifically disclose each memory die in the stack of memory dies further includes one or more deep trench capacitors formed within the semiconductor substrate. However, Chen discloses (see, for example, FIG. 1D-1E) a device comprising a deep trench capacitor 150 formed within a semiconductor substrate 110B’. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to include one or more deep trench capacitors formed within the semiconductor substrate for power decoupling, and reducing noise and leakage current within the memory device.
Claim(s) 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2013/0021866 A1 as applied to claim 1-3 above, and further in view of Ken et al. US 2013/0091315 A1. Lee does specifically disclose the stack of memory dies being vertically stacked on top of a logic die. However, Ken discloses (see, for example, FIG. 5) a memory device 100 comprising a stack of memory dies 102/104 being vertically stacked on top of a logic die 106. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the stack of memory dies being vertically stacked on top of a logic die in order to control the memory arrays with improved density and smaller packaging footprint.
Regarding claim 12, Lee does not disclose the logic die being connected to at least
one of an interposer or a package substrate; however, Ken discloses a memory device comprising a stack of memory dies 102/104, logic die 106, and substrate 114. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a substrate in order to support the entire memory device, and make further connections therein according to the preferences of the user.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 5, 7, 8, and 10-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Eugene Lee
/EUGENE LEE/Primary Examiner, Art Unit 2815
August 18, 2026
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