Prosecution Insights
Last updated: August 18, 2026
Application No. 18/382,546

SEMICONDUCTOR DEVICE HAVING THROUGH-VIA STRUCTURE

Final Rejection §103
Filed
Oct 23, 2023
Priority
Nov 29, 2022 — RE 10-2022-0163253
Examiner
LEE, EUGENE
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
748 granted / 914 resolved
+13.8% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
42 currently pending
Career history
947
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
59.9%
+19.9% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
13.3%
-26.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 914 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, and 3 thru 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Itaya et al. US 2011/0084385 A1 in view of Park et al. US 2015/0102497 A1. Itaya discloses (see, for example FIG. 4) a semiconductor device comprising a semiconductor substrate 80, integrated circuit layer 81a/81, first metal wiring layer P0, n-th metal wiring metal wiring layer P1, P2, P3, etc., plurality of wiring vias TH0/TH1/TH2, through-via 1b, and via connection pad P0. The through via 1b extends from a via connection pad P0, and penetrates the semiconductor substrate 80. The via connection pad P0 provides a cap (i.e. capping-type via connection pad) on an upper surface of the through-via 1b. Itaya does not disclose the via connection pad includes a first capping-type via connection pad and a second capping-type via connection pad, wherein the first capping-type via connection pad is formed on an entirety of the upper surface of the through-via, and the second capping-type via connection pad is formed on an entirety of the upper surface of the first capping-type via connection pad, and wherein the first capping-type via connection pad and the second capping-type via connection pad are integrally formed. However, Park discloses (see, for example, FIG. 2A) a semiconductor device comprising a via connection pad 150 includes a first capping-type via connection pad 152, and a second capping-type via connection pad 154. The first capping-type via connection pad 152 is formed on an entirety of the upper surface of the through-via 180, and the second capping-type via connection pad 154 being formed on the first capping-type via connection pad 152. In paragraph [0062], Park discloses a width of the first capping-type via connection pad 152 may be less than a width of the second capping-type via connection pad 154, and therefore, the second capping-type via connection pad 154 includes being formed on an entirety of the upper surface of the first capping -type via connection pad 152. Further, Park discloses (see, for example, paragraph [0064]) that the first capping-type via connection pad 152 and second capping-type via connection pad 154 being both made of a same material such as copper. In the limitation “integrally formed”, the term “integral” is defined by Webster’s Dictionary as “formed as a unit with another” or “composed of constituent parts”, which Park clearly discloses in the via connection pad 150. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the via connection pad includes a first capping-type via connection pad and a second capping-type via connection pad, wherein the first capping-type via connection pad is formed on an entirety of the upper surface of the through-via, and the second capping-type via connection pad is formed on an entirety of the upper surface of the first capping-type via connection pad, and wherein the first capping-type via connection pad and the second capping-type via connection pad are integrally formed in order to provide further protect the top surface of the through-via, and prevent physical defects in the semiconductor device. Further, regarding the limitation “integrally formed”, even though fully disclosed in the Park reference as cited above, for the sake of arguendo, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to use a one-piece construction including the first capping-type via connection pad and the second capping-type via connection pad in order to lessen manufacturing time, and since it would have been merely a matter of obvious engineering choice.” In re Larson, 340 F. 2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Regarding claim 3, see, for example, FIG. 2A wherein Park discloses a width of the first capping-type via connection pad 152 being greater than a width of the through-via 180. Regarding claim 4, see, for example, paragraph [0062] wherein Park discloses a width of the first capping-type via connection pad 152 may be less than a width of the second capping-type via connection pad 154. Regarding claim 5, see, for example, paragraph [0090] wherein Park discloses using any of various shapes including hexagons, circular, oval, quadrangular, etc. Further, it would have been an obvious matter of design choice, at a time prior to the effective filing date, to have an octagonal shape for the first and second capping-type via connection pad in order to fit the pad into the semiconductor device according to the preferences of the user since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Regarding claim 6, see, for example, FIG. 2A wherein Park discloses nth metal layer M1 being at a same horizontal level as the via connection pad 152. Regarding claim 7, see, for example, FIG. 2A wherein Park discloses nth metal layer M1 being at a same horizontal level as the via connection pad 152, and FIG. 4B wherein Park discloses a mesh pattern. Regarding claim 8, Itaya discloses (see, for example, FIG. 4) an upper pad 85, and a lower pad 84. Response to Arguments See the rejection for claim 1 above. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. INFORMATION ON HOW TO CONTACT THE USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Eugene Lee August 3, 2026 /EUGENE LEE/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Oct 23, 2023
Application Filed
Mar 03, 2026
Non-Final Rejection mailed — §103
Mar 27, 2026
Applicant Interview (Telephonic)
Mar 27, 2026
Examiner Interview Summary
Jun 03, 2026
Response Filed
Aug 05, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
88%
With Interview (+5.7%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 914 resolved cases by this examiner. Grant probability derived from career allowance rate.

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