Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 2, 2026 in which claims 1-2, 4-9 and 11-22 are pending has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4, 6-9, 11, 13-14, 16-19 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 2023/0215759 (Seacrist), U.S. 2017/0338321 (Hurwitz), Christensen, M., et al. “Formation of nickel-platinum silicides on a silicon substrate: Structure, phase stability, and diffusion from ab initio computations.” Journal of Applied Physics, vol. 114, no. 3, 19 July 2013, https://doi.org/10.1063/1.4816094 (Christensen) and Dennis, John R., and Edward B. Hale. “Crystalline to amorphous transformation in ion-implanted silicon: A composite model.” Journal of Applied Physics, vol. 49, no. 3, 1 Mar. 1978, pp. 1119–1127, https://doi.org/10.1063/1.325049 (Dennis).
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Regarding claim 1, Seacrist discloses at annotated Figure 2 a semiconductor-on-insulator (SOI) substrate, 20 [0012, 29], including a handle wafer, 22 [0012, 29] a buried oxide, 24 with a thickness of 0.1-10 micron (i.e., 1000 to 100,000 A) [0012, 39, 45], over said handle wafer, as shown, and a thin semiconductor layer, 26 [0012-14, 56] with a thickness of 20 nm to 3 microns [0056], over said buried oxide, as shown; said thin semiconductor layer having a first thickness less than approximately four hundred angstroms (400 Å), i.e. 20 nm is 200 A which is less than 400 A, and said buried oxide having a second thickness greater than approximately twenty times (20x) said first thickness, i.e. a 100,000 A buried oxide thickness / 200 A silicon thickness is 500x which is greater than 20x.
At [0011-13], Seacrist teaches:
[0011] The use of high resistivity semiconductor-on-insulator (e.g., silicon-on-insulator) wafers for RF related devices such as antenna switches offers benefits over traditional substrates in terms of cost and integration. To reduce parasitic power loss and minimize harmonic distortion inherent when using conductive substrates for high frequency applications it is necessary, but not sufficient, to use substrate wafers with a high resistivity. Accordingly, the resistivity of the handle wafer for an RF device is generally greater than about 500 Ohm-cm. With reference now to FIG. 1, a silicon on insulator structure 2 comprises a very high resistivity silicon wafer 4, a buried oxide (BOX) layer 6, and a silicon device layer 10. Such a substrate is prone to formation of high conductivity charge inversion or accumulation layers 12 at the BOX/handle interface causing generation of free carriers (electrons or holes), which reduce the effective resistivity of the substrate and give rise to parasitic power losses and device nonlinearity when the devices are operated at RF frequencies. These inversion/accumulation layers can be due to BOX fixed charge, oxide trapped charge, interface trapped charge, and even DC bias applied to the devices themselves.
[0012] A method is required therefore to suppress the formation of any induced inversion or accumulation layers so that the high resistivity of the substrate is maintained even in the very near surface region. It is known that trap rich layers between the high resistivity handle substrates and the buried oxide (BOX) may improve the performance of RF devices fabricated using SOI wafers. A number of methods have been suggested to form these high interface trap layers. For example, with reference now to FIG. 2, one of the method of creating a semiconductor-on-insulator multilayer structure 20 (e.g., a silicon-on-insulator, or SOI) with a trap rich layer for RF device applications is based on depositing an undoped polycrystalline silicon film 28 on a silicon substrate having high resistivity 22 and then forming a stack of oxide (e.g., buried oxide layer 24) and top silicon layer 26 on it. A polycrystalline silicon layer 28 acts as a high defectivity layer between the silicon substrate 22 and the buried oxide layer 24. See FIG. 2, which depicts a polycrystalline silicon film for use as a trap rich layer 28 between a high resistivity substrate 22 and the buried oxide layer 24 in a silicon-on-insulator multilayer structure 20. An alternative method is the implantation of heavy ions to create a near surface damage layer. Devices, such as radiofrequency devices, are built in the top silicon layer 26.
[0013] It has been shown in academic studies that the polycrystalline silicon layer between of the oxide and substrate improves the device isolation, decreases transmission line losses and reduces harmonic distortions. See, for example: H. S. Gamble, et al. “Low-loss CPW lines on surface stabilized high resistivity silicon,” Microwave Guided Wave Lett., 9(10), pp. 395-397, 1999; D. Lederer, R. Lobet and J. P. Raskin, “Enhanced high resistivity SOI wafers for RF applications,” IEEE Intl. SOI Conf, pp. 46-47, 2004; D. Lederer and J. P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity,” IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, 2005; D. Lederer, B. Aspar, C. Laghaé and J. P. Raskin, “Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate,” IEEE International SOI Conference, pp. 29-30, 2006; and Daniel C. Kerr et al. “Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer”, Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008 (IEEE Topical Meeting), pp. 151-154, 2008.
At [0023-24], Seacrist teaches;
[0023] According to the present invention, a method is provided and a structure is provided for producing semiconductor-on-insulator (e.g., silicon-on-insulator) structures that enables superior radio frequency (RF) device performance, device stability, and device fabrication manufacturability. The present invention integrates a high resistivity, e.g. a very-high resistivity or a ultra-high resistivity, float zone (FZ) silicon base wafer (handle wafer) and a trap rich layer into a semiconductor-on-insulator (e.g., silicon-on-insulator) structure.
[0024] Radio frequency (RF) chip designs significantly benefit from higher substrate resistivity levels. Improvements in the quality factor of passive components, such as inductors and capacitors, reduced attenuation in transmission lines, and substrate electrical isolation between the integrated digital, RF, and analog components are realized with higher resistivity silicon substrates. The industry standard is handle substrate resistivity above 1,000 ohm-cm, with yet higher resistivity preferred. Integration of the high resistivity substrate into semiconductor-on-insulator (e.g., silicon-on-insulator) structure (HRSOI) further improves RF capability by providing better device isolation, reduced conductive coupling to the substrate wafer, and lower junction capacitance.
At [0045], Seacrist teaches:
[0045] In some embodiments, deposition of the trap rich layer is followed by formation of a dielectric layer on the surface of the trap rich layer. In some embodiments, the single semiconductor handle substrate (e.g., single crystal silicon handle substrate) is oxidized to form a semiconductor oxide (e.g., a silicon dioxide) film on the trap rich layer. In some embodiments, the trap rich layer, e.g., polycrystalline film, may be thermally oxidized (in which some portion of the deposited semiconductor material film will be consumed) or the semiconductor oxide (e.g., silicon dioxide) film may be grown by CVD oxide deposition. The oxide layer (e.g., silicon dioxide layer) in contact with the polycrystalline or amorphous trap rich layer (e.g., a polycrystalline or amorphous silicon trap rich layer) may have a thickness between about 0.1 micrometer and about 10 micrometers, such as between about 0.1 micrometers and about 4 micrometers, such as between about 0.1 micrometers and about 2 micrometers, or between about 0.1 micrometers and about 1 micrometer. The oxidation process additionally oxidizes the back surface of the single crystal semiconductor handle wafer, which advantageously reduces warp and bow potentially caused by the different coefficients of thermal expansion of silicon and silicon dioxide.
At [0056], Seacrist teaches;
[0056] After the cleave and high temperature anneal, the bonded structure may be subjected to a cleaning process designed to remove thin thermal oxide and clean particulates from the surface. In some embodiments, the single crystal semiconductor device layer may be brought to the desired thickness and smoothness by subjecting to a vapor phase HCl etch process in a horizontal flow single wafer epitaxial reactor using H.sub.2 as a carrier gas. In some embodiments, the semiconductor device layer 26 may have a thickness between about 20 nanometers and about 3 micrometers, such as between about 20 nanometers and about 2 micrometers, such as between about 20 nanometers and about 1.5 micrometers or between about 1.5 micrometers and about 3 micrometers.
At [0063-64], Seacrist teaches;
[0063] Radiofrequency (RF) testing was performed on several SOI structures having FZ handle substrates. The top silicon layer of the SOI wafer was removed (via wet chemical etching) and co-planar waveguide structures were fabricated directly on the BOX layer. The second harmonic distortion (HD2) and the third harmonic distortion (HD3) were measured vs input power at input powers up to 35 dBm. Devices were tested across the diameter of the wafer to determine radial uniformity of results. The results were then compared to similarly fabricated-planar waveguide structures on SOI wafers having handle substrates prepared by the Czochralski method.
[0064] FIG. 8 shows the HD2 performance of our first and second generation SOI wafers having handle substrates prepared by the Czochralski method. The HD2 at Pin=15 dBm for these wafers are −80 dBm and −90 dBm, respectively. By contrast, the HD2 of the SOI structures having FZ handle substrates shows a dramatic improvement 20 dBm to a value of −110 dBm at Pin=15 dBm. The difference in performance is driven by the difference in resistivity between the typical CZ wafer and the FZ wafers. HD2 was measured on multiple sites on the wafers and no strong radial variation in HD2 was observed. The SOI structures having FZ handle substrates consistently had better performance than the SOI wafers having handle substrates prepared by the Czochralski method.
Seacrist teaches an SOI substrate with dramatic improvement in second harmonic distortion, e.g., 20 dBm [0064]. Examiner understands Seacrist teaches an SOI substrate with superior performance, stability and manufacturability. Seacrist teaches the buried oxide thickness ranges from 0.1 to 10 microns.
Seacrist does not teach a radio frequency switch comprising a transistor in said thin semiconductor layer, said transistor including a gate, a source, a drain; said transistor; nickel silicides on said source and said drain, said nickel silicides in an upper portion of said thin semiconductor layer, said source and drain being monocrystalline semiconductor material.
Hurwitz is directed to RF switches using SOI substrates. Hurwitz teaches at annotated Figure 3H a semiconductor-on-insulator (SOI) substrate, 301/302/303 [0028], including a handle wafer, 301 [0028], a buried oxide, 302 [0028], over said handle wafer, as shown, and a thin semiconductor layer, 303 [0028], over said buried oxide, as shown; a transistor, 300 [0027], in said thin semiconductor layer, as shown, said transistor including a gate, 307 [0029], a source, 304A [0032], a drain, 305A [0032]; nickel silicides, 331-333 [0037-38], on said source and said drain, as shown, said nickel silicides in an upper portion of said thin semiconductor layer, as shown.
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Hurwitz teaches nickel silicide with a platinum additive are to be formed on the source drain regions to improve device performance, i.e. meet noise requirements of an LNA [0047].
Hurwitz does not explicitly teach said source and said drain being monocrystalline material.
Christensen is directed to the chemistry
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and physics of nickel silicide formation with Pt additives over a silicon substrate. Christensen reports that Ni formed on amorphous silicon forms mostly the NiSi2 phase which has undesirable resistivity. Further in the case of a crystalline silicon substrate, that Pt will preferentially segregate to the silicon crystal lattice surfaces, low energy sites, which stabilizes the formation of the desired NiSi phase. At Figure 6, Christensen teaches that Ni in the presence of Pt on a crystalline silicon surface proceeds to form the desirable NiSi phase at the conclusion of silicidation.
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Dennis is directed to modeling and measurement of ion implant processes which amorphize monocrystalline silicon. At Table II, Dennis reports that a critical dose of a heavy ion, e.g., Kr, is less than 0.5E14 cm/2 at 20 Kev at 300 K which preserves silicon crystallinity. At Figure 5, Dennis teaches a variety of doses and energies for heavy ions, e.g. As, that preserve silicon crystallinity. (Kr has an atomic weight of ~84 and As has an atomic weight of ~75).
Taken as a whole, the prior art is directed to improvements in RF switching devices. Seacrist teaches an SOI substrate for RF devices which has a dramatic improvement in second order harmonics. Hurwitz teaches an RF switch using a SOI substrate integrating nickel silicide has an advantage of meeting noise requirements for a low noise amplifier [0046]. Christensen teaches silicidation on a crystalline silicon surface with an addition of Pt stabilizes the desirable NiSi phase while inhibiting formation of the undesirable NiSi2 phase. Dennis teaches Hurwitz’s source drain regions may be preserve Seacrist’s monocrystalline structure with an implant dose less than a critical energy and fluence. An artisan would find it desirable to produce an RF switch with dramatically improved second harmonic distortion and low noise using a substrate with superior performance, stability and manufacturability.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to use Seacrist’s SOI substrate to configure a radio frequency switch comprising a transistor in said thin semiconductor layer, said transistor including a gate, a source, a drain; said transistor; nickel silicides on said source and said drain, said nickel silicides in an upper portion of said thin semiconductor layer, as taught by Hurwitz, said source and drain being monocrystalline semiconductor material, as taught be Christensen to produce a low resistivity silicide phase and in turn to produce a device with improved source/drain contact resistance, dramatically improved harmonic distortion and low noise input to a LNA and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Furthermore, Examiner takes the position that in reference to the claim language referring to the functions of the device, i.e., "so as to increase maximum power handling (PMAX) of said transistor", intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78 (Fed. Cir. 1997). This is because “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, (Fed. Cir. 1990). If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); see MPEP 2114.
In the instant case and as explained above, the modified prior art shows all structural limitations specifically recited in the claim. From Applicant’s explanation of the functioning of the claimed device (as set forth in Applicant’s specification), it appears that any device having the specifically recited structural limitations could perform the recited function. Accordingly, it appears that the recited functional limitation does not affect the structure of modified prior art device and so it meets the claim.
Regarding claim 2 which depends upon claim 1, Hurwitz teaches said nickel silicides include at least one additive selected from the group consisting of molybdenum (Mo) and platinum (Pt) at [0034].
Regarding claim 4, which depends upon claim 1, Seacrist teaches the SOI substrate further includes a trap-rich layer, 28 [0012] under said buried oxide.
Regarding claim 21 which depends upon claim 4, Seacrist teaches the trap-rich layer comprises polycrystalline silicon (polysilicon) at [0012].
Regarding claim 6 which depends upon claim 1, Seacrist teaches said thin semiconductor layer is monocrystalline [0030, 57] and Hurwitz teaches said thin semiconductor layer is monocrystalline at [0028].
Regarding claim 7 and referring to the discussion at claim 1, Seacrist discloses a method of providing an improved SOI substrate for RF switches comprising providing a semiconductor-on-insulator SOI substrate, 20 [0012], including a handle wafer, 22 [0012, 29], a buried oxide layer, 24 [0012, 29], over said handle wafer, as shown, and a thin semiconductor layer 26 [0012, 56] e.g., 20 nm, over said buried layer, 24, wherein said thin semiconductor layer having a first thickness less than approximately 400 A, e.g., 200 A [0056], and said buried oxide having as second thickness, e.g. 100,000 A [0039, 45] greater than approximately twenty times (20x) said first thickness, i.e., 500x is greater than 20x.
Seacrist does not teach forming a gate of a transistor over said thin semiconductor layer, forming a source and a drain of said transistor in said thin semiconductor layer, said forming said source and said drain of said transistor comprising implanting ions in said thin semiconductor layer without amorphizing said thin semiconductor layer.
Hurwitz teaches a process of using a SOI substrate to form a RF switch comprising forming a gate of a transistor over said thin semiconductor layer, forming a source and a drain of said transistor in said thin semiconductor layer, said forming said source and said drain of said transistor comprising implanting ions in said thin semiconductor layer [0030].
Hurwitz teaches NiSi is useful on source drain regions to meet noise requirements of a LNA [0046].
Hurwitz does not explicitly teach implanting ions in said thin semiconductor layer without amorphizing said thin semiconductor layer.
Christenson teaches that a desirable nickel silicide phase is produced during silicidation of a crystalline silicon.
Dennis teaches a method of implanting to preserve the crystal structure of a semiconductor material, i.e., without amorphorizing the semiconductor material.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure a method to form a RF switch by using Seacrist’s SOI substrate with improved harmonic noise reduction and by forming a gate of a transistor over said thin semiconductor layer, forming a source and a drain of said transistor in said thin semiconductor layer, said forming said source and said drain of said transistor comprising implanting ions in said thin semiconductor layer, as taught by Hurwitz to meet LNA noise requirements as taught by Hurwtiz, without amorphizing said thin semiconductor layer, as taught by Dennis, to produce an RF switch with low source-drain contact resistance, as taught by Christenson, and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Examiner also takes the position that in reference to the claim language referring to the functions of the device, i.e., "so as to increase maximum power handling (PMAX) of said transistor", intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78 (Fed. Cir. 1997). This is because “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, (Fed. Cir. 1990). If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); see MPEP 2114.
In the instant case and as explained above, the modified prior art shows all structural limitations specifically recited in the claim. From Applicant’s explanation of the functioning of the claimed device (as set forth in Applicant’s specification), it appears that any device having the specifically recited structural limitations could perform the recited function. Accordingly, it appears that the recited functional limitation does not affect the structure of modified prior art device and so it meets the claim.
Regarding claim 8 which depends upon claim 7, Hurwitz teaches forming nickel silicides, 331-333 [0037-38], on said source and said drain in an upper portion of said thin semiconductor layer, annotated and shown.
Regarding claim 9 which depends upon claim 8, Hurwitz teaches said nickel silicides include at least one additive selected from the group consisting of molybdenum (Mo) and platinum (Pt) at [0034].
Regarding claim 11, which depends upon claim 7, Seacrist teaches the SOI substrate further includes a trap-rich layer, 28 [0012] under said buried oxide.
Regarding claim 22 which depends upon claim 7, Seacrist teaches the trap-rich layer comprises polycrystalline silicon (polysilicon) at [0012].
Regarding claim 13 which depends upon claim 7, Seacrist teaches said thin semiconductor layer is monocrystalline [0030, 57] and Hurwitz teaches said thin semiconductor layer is monocrystalline at [0028].
Regarding claim 14, Seacrist teaches a semiconductor-on-insulator (SOI) substrate, 20 [0012], including a handle wafer, 22 [0012, 29], a thick buried oxide, 24 [0012, 39, 45], over said handle wafer as shown, a thin semiconductor layer, 26 [0012, 56], over said buried oxide layer, as shown, said thin semiconductor layer having a thickness less than approximately four hundred angstrom (400 A), e.g., 20 nm or 200 A, and said buried oxide having a second thickness, e.g. 100,000 A, greater than approximately twenty times (20x) said first thickness, e.g., 500x. Seacrist teaches the thin semiconductor layer is monocrystalline at [0030, 57]
Seacrist does not teach a transistor in said thin semiconductor layer, said transistor including a gate, a source, a drain, said source and said drain being a monocrystalline semiconductor material.
Referring to the discussion at claim 1, Hurwitz teaches a SOI substrate comprising a transistor in said thin semiconductor layer, said transistor including a gate, a source, a drain.
Hurwitz teaches nickel silicide with a platinum additive are to be formed on the source drain regions to improve device performance, i.e. meet noise requirements of an LNA [0047].
Hurwitz does not explicitly teach said source and said drain being monocrystalline semiconductor material.
As discussed above, Christensen teaches a favorable phase of nickel silicide is formed on a monocrystalline silicon layer.
As discussed above, Dennis teaches the crystal structure of a semiconductor may be preserved during an ion implant process.
Taken as a whole, the prior art is directed to improvements in RF SOI devices. Seacrist teaches a SOI substrate with dramatically improved second harmonics. Hurwitz teaches an RF SOI device with nickel silicide contacts meets the noise requirements of an LNA. Christensen teaches that a desirable phase of nickel silicide is formed on a monocrystalline semiconductor material. Dennis teaches that the crystal structure of a semiconductor material may be preserved with suitable dose, energy and fluence during implant. An artisan would find it desirable to configure a RF switching device with improve harmonic which meet a LNA noise requirements.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 14 comprising a transistor in said thin semiconductor layer, said transistor including a gate, a source, a drain, said source and said drain being a monocrystalline semiconductor material to produce a RF device with improved harmonic performance and low noise and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Examiner also takes the position that in reference to the claim language referring to the functions of the device, i.e., "so as to increase maximum power handling (PMAX) of said transistor", intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78 (Fed. Cir. 1997). This is because “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, (Fed. Cir. 1990). If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); see MPEP 2114.
In the instant case and as explained above, the modified prior art shows all structural limitations specifically recited in the claim. From Applicant’s explanation of the functioning of the claimed device (as set forth in Applicant’s specification), it appears that any device having the specifically recited structural limitations could perform the recited function. Accordingly, it appears that the recited functional limitation does not affect the structure of modified prior art device and so it meets the claim.
Regarding claim 16 which depends upon claim 14, Hurwitz teaches said at least one RF device comprises a low noise amplifier (LNA) at [0014, 27].
Regarding claim 17 which depends upon claim 14, Hurwitz teaches nickel silicides, 331-333 [0037-38], on said source and said drain in an upper portion of said thin semiconductor layer.
Regarding claim 18 which depends upon claim 17, Hurwitz teaches said nickel silicides include at least one additive selected from the group consisting of molybdenum (Mo) and platinum (Pt) at [0034].
Regarding claim 19 which depends upon claim 14, Secrist teaches said SOI substrate further includes a trap-rich layer, 28 [0012], under said buried oxide.
Claims 5, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Secrist, Hurwitz, Christensen, Dennis and U.S. 2025/0063822 (Singh).
Regarding claim 5 which depends upon claim 1, Hurwitz does not teach said transistor is a fully depleted transistor.
Singh is directed to RF switching devices. At [0055], Singh teaches that a fully depleted RF switching transistor reduced harmonics in applied RF signals. An artisan would find it desirable to improve signal fidelity by reducing harmonics.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 wherein said transistor is a fully depleted transistor, as taught by Singh, to reduce harmonics of applied RF signals, as taught by Singh and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 12 which depends upon claim 7, Hurwitz does not teach said transistor is a fully depleted transistor.
Singh teaches fully depleted RF switching transistors reduces RF harmonics.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 9 wherein said transistor is a fully depleted transistor, as taught by Singh, to reduce harmonics of applied RF signals, as taught by Singh and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 20 which depends upon claim 14, Hurwitz does not teach said transistor is a fully depleted transistor.
Singh teaches fully depleted RF switching transistors reduces RF harmonics.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 14 wherein said transistor is a fully depleted transistor, as taught by Singh, to reduce harmonics of applied RF signals, as taught by Singh and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Secrist, Hurwitz, Christensen, Dennis and U.S. 2023/0102053 (Xu).
Regarding claim 15 which depends upon claim 14, Hurwitz does not teach said at least one RF device comprises a single pole double throw (SPDT) switch.
Xu is directed to applications of RF switching devices at [0055] and Figure 8, Xu teaches an RF switch with a SPDT configuration.
Taken as a whole, the prior art is directed to RF switching devices. Xu teaches an RF switching device may be configures as a SPDT switch. An artisan would recognize that a SPDT RF switch offers simplicity in routing one signal between two different paths making it ideal for selecting between and antenna and a load or switching between different frequency bands in a mobile device.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 wherein said at least one RF device comprises a single pole double throw (SPDT) switch, as taught by Xu, to implement a topology to enable switching between different RF frequency bands and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Response to Arguments
In order to be entitled to reconsideration or further examination, the applicant or patent owner must reply to the Office action. The reply by the applicant or patent owner must be reduced to a writing which distinctly and specifically points out the supposed errors in the examiner's action and must reply to every ground of objection and rejection in the prior Office action. See MPEP 714.02.
Applicant’s arguments with respect to claims 1, 7 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Seacrist teaches the amended subject matter for a SOI substrate with superior RF switching performance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
Prosecution Insights