DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 23 October 2023 has been considered by the Examiner.
Claim Objections
Claim 20 is objected to because of the following informality: In Line 25, the Examiner assumes that “obtaining a m-th spectral information” should actually be --obtaining an m-th spectral information--. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the Applicant), regards as the invention.
Claim 1 recites the limitation "the same pattern" in Lines 2-3. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation to mean that each semiconductor chip has an identical pattern.
Claim 1 recites the limitation "inspecting patterns at the same first positions" in Line 8. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation as “inspecting the patterns at identical first positions”.
Claim 1 recites the limitation --inspecting patterns at the same second positions-- in Line 9. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation as “inspecting the patterns at identical second positions”.
Claim 1 recites the limitation --inspecting patterns at the same k-th positions-- in Line 10. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation as --inspecting the patterns at identical k-th positions--.
Claim 11 recites the limitation "the same pattern" in Line 2. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation to mean that each semiconductor chip has an identical pattern.
Claim 11 recites the limitation "inspecting patterns at the same first positions" in Line 10. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation as --inspecting the patterns at identical first positions--.
Claim 11 recites the limitation "inspecting patterns at the same second positions" in Line 11. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation as --inspecting the patterns at identical second positions--.
Claim 11 recites the limitation "inspecting patterns at the same k-th positions" in Line 12. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation as --inspecting the patterns at identical k-th positions--.
Claim 20 recites the limitation "the same pattern" in Line 2. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation to mean that each semiconductor chip has an identical pattern.
Claim 20 recites the limitation "inspecting patterns at the same first positions" in Line 4. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation as --inspecting the patterns at identical first positions--.
Claim 20 recites the limitation "inspecting patterns at the same second positions" in Line 6. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation as --inspecting the patterns at identical second positions--.
Claim 20 recites the limitation "inspecting patterns at the same k-th positions" in Line 8. There is insufficient antecedent basis for this limitation in the claim. Therefore, for purposes of examination, the Examiner is interpreting this limitation as --inspecting the patterns at identical k-th positions--.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims recite the abstract idea of fabricating a semiconductor device. This judicial exception is not integrated into a practical application because it is not tied to a particular machine or providing an improvement to the technology. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception, as seen in the following assessment.
Claim 1:
Preamble: A method for fabricating a semiconductor device.
A first step of loading a first wafer including a plurality of semiconductor chips having the same pattern on a stage of a wafer inspection apparatus.
A second step of inspecting the plurality of semiconductor chips using light having different wavelengths from each other.
A third step of unloading the first wafer from the stage of the wafer inspection apparatus.
Wherein inspecting of the plurality of semiconductor chips using the light includes:
a) Inspecting patterns at the same first positions of the respective semiconductor chips;
b) Inspecting patterns at the same second positions of the respective semiconductor chips;
c) Inspecting patterns at the same k-th positions of the respective semiconductor chips (k ≥ 3);
d) Determining the semiconductor chip having a pattern defect by combining pattern inspection results at the first to k-th positions.
Wherein inspecting of the patterns at the first positions includes:
a) Obtaining a first plurality of pieces of spectral information at the first positions using the light;
b) Obtaining a first spectral distribution information using the first plurality of pieces of spectral information;
c) Calculating a statistical distribution region from the first spectral distribution information;
d) Obtaining a spectral information not included in the statistical distribution region among the first plurality of pieces of spectral information;
e) Determining the semiconductor chip having the spectral information not included in the statistical distribution region as a defect.
Step 1: Statutory category determination.
The claim is drawn to a “process” (method). It falls within one of the four statutory categories under 35 U.S.C. § 101.
Step 2A, Prong 1: Identify judicial exception(s) with citations to PEG groupings;
The claim recites abstract ideas:
Mathematical concepts (2019 PEG, “Mathematical relationships, mathematical formulas or equations, mathematical calculations”):
“calculating a statistical distribution region from the first spectral distribution information”
“obtaining a first spectral distribution information” (derivation/aggregation of data into a distribution)
“determining the semiconductor chip having a pattern defect by combining pattern inspection results” (combination/aggregation and comparison across positions)
Mental processes (2019 PEG, “concepts performed in the human mind including an observation, evaluation, judgment, opinion”) insofar as they are recited at a level that could be performed conceptually by a person given the data:
“determining the semiconductor chip having a pattern defect by combining pattern inspection results”
“determining the semiconductor chip having the spectral information not included in the statistical distribution region as a defect”
These clauses are data analysis, comparison, and classification steps that fall squarely within the abstract idea groupings even though the data happens to be spectral/inspection data.
Step 2A, Prong 2: Analyze integration into a practical application; discuss any claimed technological improvement; address whether extra-solution activity or field-of-use limitations are present.
Additional elements beyond the abstract ideas include:
Loading a wafer onto the stage of a wafer inspection apparatus.
Inspecting using light of different wavelengths.
Unloading the wafer.
Performing inspections at the same positions across multiple chips using the wafer inspection apparatus.
Assessment:
Particular machine: The “wafer inspection apparatus” is recited, but the claim does not specify any unconventional inspection architecture, control scheme, or improvement to the apparatus itself (e.g., no particular optical path, detector arrangement, illumination modulation, or calibration protocol is claimed). The apparatus serves as a generic tool to collect data. Mere invocation of a known inspection tool to acquire data is generally an insufficient tie to a “particular machine” for Prong 2 when the improvement lies in post-processing data. See MPEP 2106.04(d)(1) and 2106.05(f) (field-of-use and data gathering as insignificant extra-solution activity).
Transformation of an article: The steps do not transform the wafer or chips; the wafer is loaded, measured, and unloaded. Inspection and data collection alone typically constitute insignificant extra-solution activity. No physical change or manufacture is effected by the claimed steps.
Improvement to a technology or computer functioning: The claim does not recite a specific improvement to the functioning of the wafer inspection apparatus, imaging/spectroscopy technology, or any other technology. The mathematical/statistical processing (outlier detection via a “statistical distribution region” and multi-position combining) is performed on collected data and is result-oriented without reciting a concrete technical mechanism that changes how the inspection apparatus operates or how images/spectra are generated or processed at a hardware/architecture level.
Other meaningful limitations: The domain constraint (semiconductor wafer inspection with multi-wavelength light; same-position comparisons; k ≥ 3) is a field-of-use limitation and does not, by itself, integrate the abstract ideas into a practical application.
Conclusion under Prong 2: The additional elements amount to (i) data gathering (loading, illuminating, measuring) and (ii) post-processing/classifying results. They do not impose a meaningful limit or effect an improvement to a technological process or system. Thus, the claim does not integrate the recited abstract ideas into a practical application.
Step 2B: Assess whether additional elements are significantly more; WURC with evidentiary considerations.
The remaining elements (wafer inspection apparatus; loading/unloading; inspecting using light of different wavelengths; inspecting at the same positions across chips) appear to be well-understood, routine, and conventional activities in the semiconductor metrology/inspection art. Multispectral or multi-wavelength inspection, die-to-die or die-to-database comparisons at corresponding positions, and inline wafer handling on a stage are standard features of optical wafer inspection and defect review systems.
However, under Berkheimer, a finding of “well-understood, routine, conventional” (WURC) must be supported by evidence of record (e.g., admissions in the specification, case law, or prior art publications).
The wafer inspection apparatus and multi-wavelength illumination are conventional/known as disclosed in Applicant’s specification (see, e.g. [0004]).
The mathematical/statistical steps (calculating a statistical distribution region; determining outliers; combining results across k positions) themselves are abstract and do not contribute an inventive concept when implemented on generic equipment. See, e.g., Electric Power Group (collect-analyze-display paradigms are abstract) and SAP v. InvestPic (statistical analysis of data is abstract). No unconventional hardware implementation, no specific algorithmic architecture tied to a particular machine’s operation (e.g., a novel on-tool pipeline that changes the functioning of the tool), and no other technical detail is recited that would amount to “significantly more.”
On this record, and pending proper evidentiary support, the additional elements are WURC and do not provide an inventive concept.
Conclusion: Eligible/ineligible under § 101.
Ineligible. The claim recites abstract ideas (mathematical concepts and mental processes) and does not integrate them into a practical application. The additional elements are, on their face, conventional inspection and handling steps constituting insignificant extra-solution activity. Absent an identified inventive concept, a rejection under 35 U.S.C. § 101 is warranted.
Claims 2-10: The dependent claims recite further steps of mathematical concepts and mental processes without tying the method to a particular machine or presenting an improvement in a technology.
Claim 11:
Preamble: A method for fabricating a semiconductor device.
Loading a wafer including a plurality of semiconductor chips having the same pattern on a stage of a wafer inspection apparatus.
Providing a first light having a plurality of wavelengths to a spectrometer.
Splitting the first light into a second light having any one wavelength of the plurality of wavelengths using the spectrometer.
Providing the second light to the wafer.
Inspecting the plurality of semiconductor chips using the second light.
Wherein inspecting of the plurality of semiconductor chips using the second light includes:
a) Inspecting patterns at the same first positions of the respective semiconductor chips;
b) Inspecting patterns at the same second positions of the respective semiconductor chips;
c) Inspecting patterns at the same k-th positions of the respective semiconductor chips (k ≥ 3);
d) Determining the semiconductor chip having a pattern defect by combining pattern inspection results at the first to k-th positions.
Wherein inspecting of the patterns at the first positions includes:
a) Obtaining a first plurality of pieces of spectral information at the first positions using the second light;
b) Obtaining a first spectral distribution information using the first plurality of pieces of spectral information;
c) Calculating a statistical distribution region from the first spectral distribution information;
d) Obtaining a spectral information not included in the statistical distribution region among the first plurality of pieces of spectral information;
e) Determining the semiconductor chip having the spectral information not included in the statistical distribution region as a defect.
Step 1: Statutory category determination.
The claim is drawn to a “process” (method). It falls within one of the four statutory categories under 35 U.S.C. § 101.
Step 2A, Prong 1: Identify judicial exception(s) with citations to PEG groupings; quote offending clauses.
The claim recites abstract ideas:
Mathematical concepts (2019 PEG, “Mathematical relationships, mathematical formulas or equations, mathematical calculations”):
“calculating a statistical distribution region from the first spectral distribution information”
“obtaining a first spectral distribution information” (derivation/aggregation of data into a distribution)
“determining the semiconductor chip having a pattern defect by combining pattern inspection results” (combination/aggregation and comparison across positions)
Mental processes (2019 PEG, “concepts performed in the human mind including an observation, evaluation, judgment, opinion”) insofar as they are recited at a level that could be performed conceptually by a person given the data:
“determining the semiconductor chip having a pattern defect by combining pattern inspection results”
“determining the semiconductor chip having the spectral information not included in the statistical distribution region as a defect”
These clauses are data analysis, comparison, and classification steps that fall squarely within the abstract idea groupings even though the data happens to be spectral/inspection data.
Step 2A, Prong 2: Analyze integration into a practical application; discuss any claimed technological improvement; address whether extra-solution activity or field-of-use limitations are present.
Additional elements beyond the abstract ideas include:
Loading a wafer onto the stage of a wafer inspection apparatus.
Providing multi-wavelength light to a spectrometer.
Splitting the multi-wavelength light to any one wavelength using the spectrometer.
Inspecting using light of the one wavelength.
Performing inspections at the same positions across multiple chips using the wafer inspection apparatus.
Assessment:
Particular machine: The “wafer inspection apparatus” and “spectrometer” are recited, but the claim does not specify any unconventional inspection architecture, control scheme, or improvement to the apparatus itself (e.g., no particular optical path, detector arrangement, illumination modulation, or calibration protocol is claimed). The apparatus serves as a generic tool to collect data. Mere invocation of a known inspection tool to acquire data is generally an insufficient tie to a “particular machine” for Prong 2 when the improvement lies in post-processing data. See MPEP 2106.04(d)(1) and 2106.05(f) (field-of-use and data gathering as insignificant extra-solution activity).
Transformation of an article: The steps do not transform the wafer or chips; the wafer is loaded and measured. Inspection and data collection alone typically constitute insignificant extra-solution activity. No physical change or manufacture is effected by the claimed steps.
Improvement to a technology or computer functioning: The claim does not recite a specific improvement to the functioning of the wafer inspection apparatus, imaging/spectroscopy technology, or any other technology. The mathematical/statistical processing (outlier detection via a “statistical distribution region” and multi-position combining) is performed on collected data and is result-oriented without reciting a concrete technical mechanism that changes how the inspection apparatus operates or how images/spectra are generated or processed at a hardware/architecture level.
Other meaningful limitations: The domain constraint (semiconductor wafer inspection with multi-wavelength light; same-position comparisons; k ≥ 3) is a field-of-use limitation and does not, by itself, integrate the abstract ideas into a practical application.
Conclusion under Prong 2: The additional elements amount to (i) data gathering (loading, illuminating, measuring) and (ii) post-processing/classifying results. They do not impose a meaningful limit or effect an improvement to a technological process or system. Thus, the claim does not integrate the recited abstract ideas into a practical application.
Step 2B: Assess whether additional elements are significantly more; WURC with evidentiary considerations.
The remaining elements (wafer inspection apparatus; spectrometer; loading; inspecting using light of a single wavelength; inspecting at the same positions across chips) appear to be well-understood, routine, and conventional activities in the semiconductor metrology/inspection art. Multispectral or multi-wavelength inspection, die-to-die or die-to-database comparisons at corresponding positions, and inline wafer handling on a stage are standard features of optical wafer inspection and defect review systems.
However, under Berkheimer, a finding of “well-understood, routine, conventional” (WURC) must be supported by evidence of record (e.g., admissions in the specification, case law, or prior art publications).
The wafer inspection apparatus, multi-wavelength illumination, and spectrometer are conventional/known as disclosed in Applicant’s specification (see, e.g. [0004,0008]).
The mathematical/statistical steps (calculating a statistical distribution region; determining outliers; combining results across k positions) themselves are abstract and do not contribute an inventive concept when implemented on generic equipment. See, e.g., Electric Power Group (collect-analyze-display paradigms are abstract) and SAP v. InvestPic (statistical analysis of data is abstract). No unconventional hardware implementation, no specific algorithmic architecture tied to a particular machine’s operation (e.g., a novel on-tool pipeline that changes the functioning of the tool), and no other technical detail is recited that would amount to “significantly more.”
On this record, and pending proper evidentiary support, the additional elements are WURC and do not provide an inventive concept.
Conclusion: Eligible/ineligible under § 101.
Ineligible. The claim recites abstract ideas (mathematical concepts and mental processes) and does not integrate them into a practical application. The additional elements are, on their face, conventional inspection and handling steps constituting insignificant extra-solution activity. Absent an identified inventive concept, a rejection under 35 U.S.C. § 101 is warranted.
Claims 12-19: The dependent claims recite further steps of mathematical concepts and mental processes without tying the method to a particular machine or presenting an improvement in a technology.
Claim 20:
Preamble: A method for fabricating a semiconductor device.
Loading a wafer including a plurality of semiconductor chips having the same pattern on a stage of a wafer inspection apparatus that uses multi-wavelength light.
Inspecting patterns at the same first positions of the respective semiconductor chips;
Inspecting patterns at the same second positions of the respective semiconductor chips;
Inspecting patterns at the same k-th positions of the respective semiconductor chips (k ≥ 3);
Determining the semiconductor chip having a pattern defect by combining pattern inspection results at the first to k-th positions.
Wherein inspecting of the patterns at the first positions includes:
a) Obtaining a first plurality of pieces of spectral information at the first positions using the light;
b) Obtaining a first spectral distribution information using the first plurality of pieces of spectral information;
c) Calculating a statistical distribution region from the first spectral distribution information;
d) Obtaining a spectral information not included in the statistical distribution region among the first plurality of pieces of spectral information;
e) Determining the semiconductor chip having the spectral information not included in the statistical distribution region as a defect.
Wherein obtaining of the first plurality of pieces of spectral information at the first positions using the light comprises:
obtaining a first spectral information at the first position of a first semiconductor chip,
obtaining a m-th spectral information at the first position of a j-th semiconductor chip (j ≥ 3, m≥ 3), and
obtaining the first plurality of pieces of spectral information by combining the first to m-th spectral information.
Wherein obtaining of the first spectral distribution information using the first plurality of pieces of spectral information comprises:
calculating a first distribution center which is a distribution center of the pieces of spectral information included in the first plurality of pieces of spectral information, and
obtaining the first spectral distribution information using an extent to which each of the first plurality of pieces of spectral information is separated from the first distribution center.
Step 1: Statutory category determination.
The claim is drawn to a “process” (method). It falls within one of the four statutory categories under 35 U.S.C. § 101.
Step 2A, Prong 1: Identify judicial exception(s) with citations to PEG groupings; quote offending clauses.
The claim recites abstract ideas:
Mathematical concepts (2019 PEG, “Mathematical relationships, mathematical formulas or equations, mathematical calculations”):
“calculating a statistical distribution region from the first spectral distribution information”
“obtaining a first spectral distribution information” (derivation/aggregation of data into a distribution)
“determining the semiconductor chip having a pattern defect by combining pattern inspection results” (combination/aggregation and comparison across positions)
Mental processes (2019 PEG, “concepts performed in the human mind including an observation, evaluation, judgment, opinion”) insofar as they are recited at a level that could be performed conceptually by a person given the data:
“determining the semiconductor chip having a pattern defect by combining pattern inspection results”
“determining the semiconductor chip having the spectral information not included in the statistical distribution region as a defect”
These clauses are data analysis, comparison, and classification steps that fall squarely within the abstract idea groupings even though the data happens to be spectral/inspection data.
Step 2A, Prong 2: Analyze integration into a practical application; discuss any claimed technological improvement; address whether extra-solution activity or field-of-use limitations are present.
Additional elements beyond the abstract ideas include:
Loading a wafer onto the stage of a wafer inspection apparatus.
Inspecting using light of different wavelengths.
Performing inspections at the same positions across multiple chips using the wafer inspection apparatus.
Assessment:
Particular machine: The “wafer inspection apparatus” is recited, but the claim does not specify any unconventional inspection architecture, control scheme, or improvement to the apparatus itself (e.g., no particular optical path, detector arrangement, illumination modulation, or calibration protocol is claimed). The apparatus serves as a generic tool to collect data. Mere invocation of a known inspection tool to acquire data is generally an insufficient tie to a “particular machine” for Prong 2 when the improvement lies in post-processing data. See MPEP 2106.04(d)(1) and 2106.05(f) (field-of-use and data gathering as insignificant extra-solution activity).
Transformation of an article: The steps do not transform the wafer or chips; the wafer is loaded, measured, and unloaded. Inspection and data collection alone typically constitute insignificant extra-solution activity. No physical change or manufacture is effected by the claimed steps.
Improvement to a technology or computer functioning: The claim does not recite a specific improvement to the functioning of the wafer inspection apparatus, imaging/spectroscopy technology, or any other technology. The mathematical/statistical processing (outlier detection via a “statistical distribution region” and multi-position combining) is performed on collected data and is result-oriented without reciting a concrete technical mechanism that changes how the inspection apparatus operates or how images/spectra are generated or processed at a hardware/architecture level.
Other meaningful limitations: The domain constraint (semiconductor wafer inspection with multi-wavelength light; same-position comparisons; k ≥ 3) is a field-of-use limitation and does not, by itself, integrate the abstract ideas into a practical application.
Conclusion under Prong 2: The additional elements amount to (i) data gathering (loading, illuminating, measuring) and (ii) post-processing/classifying results. They do not impose a meaningful limit or effect an improvement to a technological process or system. Thus, the claim does not integrate the recited abstract ideas into a practical application.
Step 2B: Assess whether additional elements are significantly more; WURC with evidentiary considerations.
The remaining elements (wafer inspection apparatus; loading/unloading; inspecting using light of different wavelengths; inspecting at the same positions across chips) appear to be well-understood, routine, and conventional activities in the semiconductor metrology/inspection art. Multispectral or multi-wavelength inspection, die-to-die or die-to-database comparisons at corresponding positions, and inline wafer handling on a stage are standard features of optical wafer inspection and defect review systems.
However, under Berkheimer, a finding of “well-understood, routine, conventional” (WURC) must be supported by evidence of record (e.g., admissions in the specification, case law, or prior art publications).
The wafer inspection apparatus and multi-wavelength illumination are conventional/known as disclosed in Applicant’s specification (see, e.g. [0004]).
The mathematical/statistical steps (calculating a statistical distribution region; determining outliers; combining results across k positions) themselves are abstract and do not contribute an inventive concept when implemented on generic equipment. See, e.g., Electric Power Group (collect-analyze-display paradigms are abstract) and SAP v. InvestPic (statistical analysis of data is abstract). No unconventional hardware implementation, no specific algorithmic architecture tied to a particular machine’s operation (e.g., a novel on-tool pipeline that changes the functioning of the tool), and no other technical detail is recited that would amount to “significantly more.”
On this record, and pending proper evidentiary support, the additional elements are WURC and do not provide an inventive concept.
Conclusion: Eligible/ineligible under § 101.
Ineligible. The claim recites abstract ideas (mathematical concepts and mental processes) and does not integrate them into a practical application. The additional elements are, on their face, conventional inspection and handling steps constituting insignificant extra-solution activity. Absent an identified inventive concept, a rejection under 35 U.S.C. § 101 is warranted.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure.
Honda et al. (US 2019/0206047) disclose a method for fabricating a semiconductor device (using the apparatus 100 of Fig. 1), the method comprising:
a first step of loading a first wafer (110) including a plurality of semiconductor chips (e.g. 111-115, Fig. 2) having the same pattern (“in the semiconductor chip, there are many cases where the same pattern is repeated locally” [0047]) on a stage (121) of a wafer inspection apparatus (100) [0038];
a second step of inspecting the plurality of semiconductor chips (111-115) using light (from 131,132) having different wavelengths from each other (“The wavelength of each of the light sources may be a single wavelength” [0039]); and
a third step of unloading the first wafer (110) from the stage (121) of the wafer inspection apparatus (100) (evident final step since a wafer is loaded [0038]).
Harada et al. (US 2013/0108147) disclose a method for fabricating a semiconductor device (using the apparatus 201 of Fig. 2), the method comprising:
inspecting the plurality of semiconductor chips,
wherein inspecting of the plurality of semiconductor chips includes (Fig. 3):
inspecting patterns at the same first positions of the respective semiconductor chips,
inspecting patterns at the same second positions of the respective semiconductor chips [0067],
inspecting patterns at the same k-th positions of the respective semiconductor chips (there may be more than two image capture sites in each chip).
Kamikubo (US 2011/0114951) discloses a method for fabricating a semiconductor device (Abstract), the method comprising:
inspecting patterns of semiconductor chips on a wafer using light,
wherein inspecting of the patterns includes:
obtaining a plurality of pieces of spectral information using the light [0081].
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to HINA F AYUB whose telephone number is (571)270-3171. The Examiner can normally be reached on 9am-5pm ET Mon-Fri.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Tarifur Chowdhury can be reached on 571-272-2287. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Hina F Ayub/
Primary Patent Examiner
Art Unit 2877