DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-10, 12-18, 22, and 23) in the reply filed on December 31st, 2025 is acknowledged. Claim 25 has been withdrawn by the Applicant as being directed to non-elected invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The IDS filed on 10/24/2023 and 06/16/2024 have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor device comprising a channel layer including a two-dimensional (2D) semiconductor material.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7, 10, 12, 13, and 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maxey et al. (U.S. Pub. 2021/0391478).
In re claim 1, Maxey discloses a semiconductor device 100 comprising: a substrate 101 (see paragraph [0017] and fig. 1B); a first channel layer (lowermost 110) on the substrate 101 (see paragraph [0018] and fig. 1B), the first channel layer extending in a first direction while being spaced apart from the substrate 101, and including a two-dimensional (2D) semiconductor material (see paragraph [0019] and fig. 1B); a second channel layer (adjacent 110 above the lowermost 110) on the first channel layer, the second channel layer extending in the first direction while being spaced apart from the first channel layer, and including the 2D semiconductor material (see paragraph [0018] and fig. 1B); a gate structure (130E,130I) on the substrate 101, the gate structure extending in a second direction, which is perpendicular to the first direction, and being penetrated by the first and second channel layers 110 (see paragraph [0020] and fig. 1B); and source/drain contacts 105 on side surfaces of the gate structure (130E,130I), the source/drain contacts 105 being connected to the first and second channel layers 110 (see paragraph [0021] and fig. 1B), wherein the gate structure includes a first gate portion (lowermost 130E), which is between the substrate 101 and the first channel layer and has a first gate length, a second gate portion (130I above the lowermost 130E), which is between the first and second channel layers and has a second gate length, and a third gate portion (130E above 130I), which is on an upper surface of the second channel layer and has a third gate length, and wherein the first and third gate lengths are greater than, or less than, the second gate length (see paragraph [0020] and fig. 1B, note that the first and third gate lengths are less than the second length).
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In re claim 2, as applied to claim 1 above, Maxey discloses wherein each of the first and second channel layers includes horizontal contact surfaces, which are parallel to an upper surface of the substrate 101 and are in contact with the source/drain contacts 105, and vertical contact surfaces, which are perpendicular to the first direction and are in contact with the source/drain contacts 105 (see paragraphs [0018], [0021] and fig. 1B).
In re claim 3, as applied to claim 1 above, Maxey discloses wherein the gate structure includes a gate dielectric film, which surrounds each of the first and second channel layers, and a gate electrode, which is stacked on the gate dielectric film (see paragraph [0020]).
In re claim 4, as applied to claim 3 above, Maxey discloses wherein the gate dielectric film includes a first sub-dielectric film 112, which surrounds each of the first and second channel layers and is not interposed between the gate electrode and the source/drain contacts, and a second sub-dielectric film 122, which surrounds the first sub-dielectric film and is interposed in part between the gate electrode and the source/drain contacts (see paragraph [0020] and fig. 1B).
In re claim 7, as applied to claim 1 above, Maxey discloses the semiconductor device further comprising: a separation insulating film interposed between the substrate 101 and the gate structure (130E,130I) and between the substrate 101 and the source/drain contacts 105 (see paragraph [0017] and fig. 1B, not the substrate includes a silicon-on-insulator (SOI) structure).
In re claim 10, Maxey discloses a semiconductor device 100 comprising: a substrate 101 (see paragraph [0017] and fig. 1B); a channel layer 110 on the substrate 101, the channel layer 110 extending in a first direction while being spaced apart from the substrate 101 (see paragraph [0018] and fig. 1B), and including a two-dimensional (2D) semiconductor material (see paragraph [0019] and fig. 1B); a gate structure (130E,130I) on the substrate 101, the gate structure (130E,130I) extending in a second direction, which is perpendicular to the first direction, and being penetrated by the channel layer 110 (see paragraph [0020] and fig. 1B); and source/drain contacts 105 on side surfaces of the gate structure (130E,130I), the source/drain contacts 105 being connected to the channel layer 110 (see paragraph [0021] and fig. 1B), wherein the gate structure includes a first gate portion (lowermost 130E), which is on a bottom surface of the channel layer and has a first gate length, and a second gate portion (130I above the lowermost 130E), which is on an upper surface of the channel layer and has a second gate length greater than the first gate length, and wherein the bottom surface of the channel layer includes first horizontal contact surfaces, which are exposed by the first gate portion and are in contact with the source/drain contacts 105 (see paragraph [0020] and fig. 1B).
In re claim 12, as applied to claim 10 above, Maxey discloses wherein the channel layer includes back gate regions, which do not overlap with the first gate portion in a third direction perpendicular to an upper surface of the substrate and overlap with the second gate portion (see paragraphs [0020], [0021] and fig. 1B, note that 110 exposed by 130E and in horizontal contact with 105).
In re claim 13, as applied to claim 12 above, Maxey discloses wherein the back gate regions include the first horizontal contact surfaces (see paragraphs [0020], [0021] and fig. 1B).
In re claim 15, as applied to claim 10 above, Maxey discloses wherein the upper surface of the channel layer 110 is exposed by the second gate portion 130I and includes second horizontal contact portions, which are in contact with the source/drain contacts 105 (see paragraph [0021] and fig. 1B).
In re claim 16, as applied to claim 10 above, Maxey discloses wherein the semiconductor device further comprising: first inner spacers (lowest 112) interposed between the first gate portion and the source/drain contacts 105 (see paragraph [0022] and fig. 1B).
In re claim 17, as applied to claim 16 above, Maxey discloses wherein the semiconductor device further comprising: second inner spacers 122 interposed between the second gate portion 130I and the source/drain contacts 105, wherein a thickness of the first inner spacers 112 is greater than a thickness of the second inner spacers 122 (see paragraphs [0021], [0022] and fig. 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18, 22, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maxey et al. (U.S. Pub. 2021/0391478) in view of Frougler (U.S. Pub. 2021/0135015).
In re claim 18, Maxey discloses a semiconductor device 100 comprising: a substrate 101 (see paragraph [0017] and fig. 1B); first and second channel layers 110 sequentially stacked on the substrate 101, spaced apart from each other, extending in a first direction (see paragraph [0018] and fig. 1B), and including a two-dimensional (2D) semiconductor material (see paragraph [0019] and fig. 1B); a gate structure (130E,130I) on the substrate 101, the gate structure (130E,130I) extending in a second direction, which is perpendicular to the first direction, and being penetrated by the first and second channel layers 110 (see paragraph [0020] and fig. 1B); gate spacers (112,122) extending along side surfaces of the gate structure (130E,130I) and being penetrated by the first and second channel layers 110 (see paragraphs [0021], [0022] and fig. 1B); and source/drain contacts 105 on the side surfaces of the gate structure (130E,130I) (see paragraph [0021] and fig. 1B), wherein the gate structure includes first (lowermost 130E), second (130I), and third gate portions (adjacent 130E above 130I), which are alternately arranged with the first and second channel layers 110 in a third direction perpendicular to an upper surface of the substrate 101 (see paragraph [0020] and fig. 1B), wherein a first gate length of the first gate portion (lowermost 130E) is less than a second gate length of the second gate portion (130I), wherein the second gate length of the second gate portion 130I is greater than a third gate length of the third gate portion (adjacent 130E above 130I), and wherein the source/drain contacts 105 are in contact with bottom surfaces of the contact portions of the first channel layer (lowermost 110) and upper surfaces of the contact portions of the second channel layer (adjacent 110) (see paragraphs [0021], [0022] and fig. 1B).
Maxey discloses that the source/drain contacts 105 may be highly doped semiconductor materials or conductive materials (see paragraph [0021] and fig. 1B) but is silent to wherein the source/drain contacts including a metal material, wherein both end portions of each of the first and second channel layers include contact portions, which include the 2D semiconductor material doped with impurities.
However, Frougler discloses in a same field of endeavor, a semiconductor device, including, inter-alia, to wherein the source/drain contacts 40 including a metal material such as tungsten (see paragraph [0033] and fig. 9), wherein both end portions of each of the first and second channel layers 36 include contact portions, which include the 2D semiconductor material doped with impurities (see paragraphs [0030], [0031], [0032], [0033] and fig. 8).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Frougler into the semiconductor device of Maxey in order to enable wherein the source/drain contacts including a metal material, wherein both end portions of each of the first and second channel layers include contact portions, which include the 2D semiconductor material doped with impurities in Maxey to be formed in order to reduce contact resistance (see paragraph [0033] of Frougler). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id.
In re claim 22, as applied to claim 18 above, Maxey in combination with Frougler discloses wherein the semiconductor device further comprising: first inner spacers 112 interposed between the first gate portion (lowermost 130E) and the source/drain contacts 105 and between the third gate portion (uppermost 130E) and the source/drain contacts 105 (see paragraphs [0022], [0024] and fig. 1B of Maxey).
In re claim 23, as applied to claim 22 above, Maxey in combination with Frougler discloses wherein the semiconductor device further comprising: second inner spacers 122 interposed between the second gate portion 130I and the source/drain contacts 105, wherein a thickness of the first inner spacers 122 is greater than a thickness of the second inner spacers 122 (see paragraphs [0021], [0022], [0024] and fig. 1B of Maxey).
Claim(s) 5, 6, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maxey et al. (U.S. Pub. 2021/0391478), as applied to claims 1 and 12 above, respectively, and further in view of Frougler (U.S. Pub. 2021/0135015).
In re claim 5, as applied to claim 1 above, Maxey is silent to wherein each of the first and second channel layers includes a central portion, which includes the 2D semiconductor material, and contact portions, which are at both end portions of the central portion and include the 2D semiconductor material doped with impurities.
However, Frougler discloses in a same field of endeavor, a semiconductor device including, inter-alia, wherein each of the first and second channel layers 36 includes a central portion, which includes the 2D semiconductor material, and contact portions, which are at both end portions of the central portion and include the 2D semiconductor material doped with impurities (see paragraphs [0030], [0031], [0032], [0033] and fig. 8).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Frougler into the semiconductor device of Maxey in order to enable wherein each of the first and second channel layers includes a central portion, which includes the 2D semiconductor material, and contact portions, which are at both end portions of the central portion and include the 2D semiconductor material doped with impurities in Maxey to be formed in order to reduce contact resistance (see paragraph [0033] of Frougler).
In re claim 6, as applied to claim 5 above, Maxey in combination with Frougler discloses wherein the 2D semiconductor material includes a transition metal dichalcogenide (TMD) (see paragraph [0019] of Maxey).
In re claim 14, as applied to claim 12 above, Maxey is silent to wherein the back gate regions include the 2D semiconductor material doped with impurities.
However, Frougler discloses in a same field of endeavor, a semiconductor device including, inter-alia, wherein the back gate regions include the 2D semiconductor material doped with impurities (see paragraphs [0030], [0031], [0032], [0033] and fig. 8).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Frougler into the semiconductor device of Maxey in order to enable wherein the back gate regions include the 2D semiconductor material doped with impurities in Maxey to be formed in order to reduce contact resistance (see paragraph [0033] of Frougler).
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maxey et al. (U.S. Pub. 2021/0391478), as applied to claim 1 above, and further in view of Lin et al. (U.S. Pub. 2023/0023186).
In re claim 8, as applied to claim 1 above, Maxey is silent to wherein each of the source/drain contacts includes a contact insertion film and a contact filling film, which are sequentially stacked on side surfaces of the gate structure, and wherein each of the first and second channel layers form ohmic contacts with the contact insertion film.
However, Lin discloses in a same field of endeavor, a semiconductor device, including, inter-alia, wherein each of the source/drain contacts includes a contact insertion film 230A and a contact filling film 230B, which are sequentially stacked on side surfaces of the gate structure, and wherein each of the first and second channel layers 110 form ohmic contacts with the contact insertion film 230A (see paragraphs [0071], [0072], [0073], [0074] and fig. 21).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Lin into the semiconductor device of Maxey in order to enable wherein each of the source/drain contacts includes a contact insertion film and a contact filling film, which are sequentially stacked on side surfaces of the gate structure, and wherein each of the first and second channel layers form ohmic contacts with the contact insertion film in Maxey to be formed because in doing so the contact resistance between the source/drain contacts and the first and second channel layers may be reduced and thus device performance may be improved.
In re claim 9, as applied to claim 8 above, Maxey in combination with Lin discloses wherein the contact insertion film includes a semimetal material (see paragraph [0071] of Lin).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cheng et al. (U.S. Pub. 2022/0399439) discloses a semiconductor device comprising a plurality of nanosheet channels (114,118,122) adjacent to a source/drain 132 (see paragraph [0073] and figs. 9A-C).
Chang et al. (U.S. Pub. 2014/0151639) discloses semiconductor device comprising a plurality of nanowires channels 120N adjacent to source regions (120S,130S) and drain regions (120D,130D) (see paragraph [0127] and fig. 13B).
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892