DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Three-dimensional (3D) trenched metal-oxide-semiconductor field-effect transistor (MOSFET) device including first doped wells and second doped wells and method for fabricating the same.
Claim Objections
Claims 1, 8, 10 are objected to because of the following informalities:
In claim 1, line 22, “the insulation layer” should be change to --the patterned insulation layer-- for consistency.
In claim 8, line 27, “the insulation layer” should be change to --the patterned insulation layer-- for consistency.
In claim 10, line 9, “the insulation layer” should be change to --the patterned insulation layer-- for consistency.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 7-10, 13, and 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sampath et al. (U.S. Pub. 2024/0234567).
In re claim 1, Sampath discloses a three-dimensional (3D) trenched metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising: a semiconductor substrate 110 (see paragraph [0075] and figs. 1A-2B); an epitaxial layer 120, having a first conductivity type (N-type), formed on the semiconductor substrate 110 (see paragraph [0075] and figs. 1A-2B); a doped area 170, first doped wells 140a, and second doped wells 140c, having a second conductivity type (P-type) opposite to the first conductivity type, formed in the epitaxial layer, wherein the first doped wells 140a are connected with the second doped wells 140c through the doped area 170 (see paragraphs [0076], [0075], [0084] and figs. 1A-2B, note that, the shielding structure 140a herein interprets as the first doped well is in electrical connection with the doped area 170); a trenched gate (180,18a,184a), formed in the epitaxial layer 120 and the first doped wells 140a, penetrating through the doped area 170a and surrounding the second doped wells 140c, wherein the trenched gate (180,182a,184a) has intersecting portions that are respectively formed in the first doped wells 140a and bottoms of the first doped wells 140a and the second doped wells 140c are lower than a bottom of the trenched gate (180,182a,184a) (see paragraph [0076] and figs. 1A-2B); first heavily-doped areas 160, having the first conductivity type (N-type), formed in the doped area 170, wherein the first heavily-doped areas 160 respectively surround the second doped wells 140c and the trenched gate (180,182a,184a) surrounds the first heavily-doped areas 160 (see paragraph [0077] and figs. 1A-2B); a patterned insulation layer 186 covering the trenched gate (180,182a,184a) to expose the first heavily-doped areas 160 and the second doped wells 140c (see paragraph [0077] and figs. 1A-2B); and a conduction layer 196 formed on the insulation layer 186, the first heavily-doped areas 160, and the second doped wells 140c (see paragraph [0077] and figs. 1A-2B).
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In re claim 2, as applied to claim 1 above, Sampath discloses wherein the trenched gate comprises a gate electrode 184a and a gate oxide layer 182a, the gate oxide layer 182a separates each of the epitaxial layer 120, the doped area 170 and the first heavily-doped area 160 from the gate electrode 184a (see paragraphs [0076], [0077] and figs. 1A-2B), and the patterned insulation layer 186 covers the gate electrode 184a and the gate oxide layer 182a (see paragraph [0077] and fig. 2A).
In re claim 3, as applied to claim 1 above, Sampath discloses wherein the 3D trenched MOSFET device further comprising second heavily-doped areas 174 respectively formed in the second doped wells 140c and electrically connected to the conduction layer 196, wherein the second heavily-doped areas 174 have the second conductivity type (P-type) (see paragraph [0075] and fig. 2A).
In re claim 5, as applied to claim 1 above, Sampath discloses wherein the first conductivity type is an N type and the second conductivity type is a P type (see paragraph [0075]).
In re claim 7, as applied to claim 1 above, Sampath discloses wherein the semiconductor substrate 10 and the epitaxial layer 120 comprise 4H (hexagonal)-SiC monocrystal (see paragraph [0075] and figs. 1A-2B).
In re claim 8, Sampath discloses a method for fabricating a three-dimensional (3D) trenched metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising: forming an epitaxial layer 120 with a first conductivity type (N-type) on a semiconductor substrate 110 (see paragraph [0075] and figs. 1A-2B); forming a doped area 170 with a second conductivity type (P-type) opposite to the first conductivity type in the epitaxial layer 120 (see paragraph [0075] and figs. 1A-2B); forming a heavily-doped region 160 with the first conductivity type (N-type) in the doped area 170 (see paragraph [0077] and figs. 1A-2B); forming first doped wells 140a and second doped wells 140c with the second conductivity type (P-type) in the epitaxial layer 120, wherein the first doped wells 140a and the second doped wells 140c penetrate through the doped area 170 and the heavily-doped region 160 (see paragraphs [0075], [0084] and figs. 1A-2B); forming a trenched gate (180,182a,184a) in the epitaxial layer and the first doped wells 140a, wherein the trenched gate (180,182a,184a) penetrates through the doped area 170 and the heavily-doped region 160 and surrounds the second doped wells 140c, thereby forming first heavily-doped areas 160 with the first conductivity type in the doped area 170 (see paragraph [0077] and figs. 1A-2B), the trenched gate (180,182a,184a) has intersecting portions that are respectively formed in the first doped wells 140a, bottoms of the first doped wells 140a and the second doped wells 140c are lower than a bottom of the trenched gate (180,182a,184a) (see paragraphs [0077], [0084] and figs. 1A-2B), the first heavily-doped areas 160 respectively surround the second doped wells 140c, and the trenched gate (180,182a,184a) surrounds the first heavily-doped areas 140a (see paragraphs [0077], [0084] and figs. 1A-2B, 4A, and 4D); forming a patterned insulation layer 186 to cover the trenched gate (180,182a,184a), thereby exposing the first heavily-doped areas 160 and the second doped wells 140c (see paragraph [0077] and figs. 1A-2B); and forming a conduction layer 196 on the insulation layer 186, the first heavily-doped areas 160, and the second doped wells 140c (see paragraph [0077] and figs. 1A-2B).
In re claim 9, as applied to claim 8 above, Sampath discloses wherein the step of forming the trenched gate (180,182a,184a) in the epitaxial layer and the first doped wells 140a comprises: forming in the epitaxial layer and the first doped wells a trench 180 that penetrates through the doped area 170 and the heavily-doped region 160 and surrounds the second doped wells 140c, wherein the trench 180 has intersecting portions that are respectively formed in the first doped wells 140a, the bottoms of the first doped wells 140a and the second doped wells 140c are lower than a bottom of the trench 180, and the trench 180 surrounds the first heavily-doped areas 160 (see paragraphs [0076], [0077] and figs. 1A-2B); forming a gate oxide layer 182a in the trench 180 and on the first heavily-doped areas 160, the first doped wells 140a, and the second doped wells 140c; forming a gate electrode 184a on the gate oxide layer 182a in the trench 180; and removing the gate oxide layer 182a on the first heavily-doped areas 160, the first doped wells 140a, and the second doped wells 140c to form the trenched gate in the epitaxial layer and the first doped wells 140a (see paragraphs [0077], [0081] and figs. 1A-2B).
In re claim 10, as applied to claim 8 above, Sampath discloses wherein after the step of forming the second doped wells 140c, second heavily-doped areas 174 having the second conductivity type (P-type) are respectively formed in the second doped wells 140c (see paragraph [0075] and fig. 2A); in the step of forming the patterned insulation layer 286 to cover the trenched gate (180,182a,184a), the patterned insulation layer 186 is formed to cover the trenched gate, thereby exposing the first heavily-doped areas 160, the second doped wells 140c, and the second heavily-doped areas 174 (see paragraph [0077] and fig. 2A); and in the step of forming the conduction layer 196 on the insulation layer 286, the first heavily-doped areas 160, and the second doped wells 140c, the conduction layer 196 is formed on the patterned insulation layer 286, the first heavily-doped areas 160, the second doped wells 140c, and the second heavily-doped areas 174 (see paragraph [0077] and fig. 2A).
In re claim 13, as applied to claim 8 above, Sampath discloses wherein the first conductivity type is an N type and the second conductivity type is a P type (see paragraph [0075] and figs. 1A-2B).
In re claim 15, as applied to claim 8 above, Sampath discloses wherein the semiconductor substrate 110 and the epitaxial layer 120 comprise 4H (hexagonal)-SiC monocrystal (see paragraph [0075] and figs. 1A-2B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sampath et al. (U.S. Pub. 2024/0234567).
In re claims 4 and 11, as applied to claims 1 and 8 above, respectively, Sampath discloses wherein the trenched gate has a hexagonal column shape (see paragraph [0141]) but is silent to wherein each of the first doped well and the second doped well has a shape of a cube or a hexagonal column
However, it is respectfully submitted that, the configuration regarding about the shapes of the first doped well and the second doped well were a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)).
Claim(s) 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sampath et al. (U.S. Pub. 2024/0234567) in view of Karmous (U.S. Pub. 2021/0111276).
In re claims 6 and 14, as applied to claims 1 and 8 above, respectively, Sampath discloses wherein the first conductivity type is an N type and the second conductivity type is a P type (see paragraph [0075]) but is silent to wherein the first conductivity type is a P type and the second conductivity type is an N type.
However, Karmous discloses in a same field of endeavor, a three-dimensional (3D) trenched metal-oxide-semiconductor field-effect transistor (MOSFET) including, inter-alia, wherein the first conductivity type is an N type and the second conductivity type a P type or vice versa since the doping types may be reversed to obtain a device that operates on a similar working principle (see paragraph [0094]).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the teaching as taught by Karmous into the three-dimensional (3D) trenched metal-oxide-semiconductor field-effect transistor (MOSFET) of Sampath in order to enable wherein the first conductivity type is a P type and the second conductivity type is an N type in Sampath to be formed since the doping types may be reversed to obtain a device that operates on a similar working principle (see paragraph [0094] of Karmous).
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ebiike et al. U.S. Patent 11,984,492 May 14, 2024.
Moon et al. U.S. Pub. 2022/0336602 October 20, 2022.
Hsieh U.S. Pub. 2016/0104702 April 14, 2016.
Cheng et al. U.S. Pub. 2016/0005837 January 7, 2016.
Matthew et al. U.S. Patent 8,786,013 July 22, 2014.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892