DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-15 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al (US 2020/0381545 A1) in view of Lee et al (12,040,383 B2).
Regarding claim 1, Chiang et al discloses a method of manufacturing an electronic device (Figure 16B), the method comprising: forming a multilayer inner spacer (Figure 16B, references 240, 242 and 260) comprising an inner layer (Figure 16B, reference 240), a middle layer (Figure 16B, reference 242), and an outer layer (Figure 16B, reference 260) within a structure formed on a top surface of a substrate (Figure 16B, reference 202), the structure comprising a plurality of semiconductor material layers (Figure 16B, reference 206) and a corresponding plurality of channel layers (Figure 16B, reference 208) alternatingly arranged in a plurality of stacked pairs (Figure 16B, references 206 and 208), the plurality of semiconductor material layers comprising silicon germanium (SiGe) (Figure 16B, reference 206; paragraph 0018) and the corresponding plurality of channel layers comprising silicon (Si) (Figure 16B, reference 208; paragraph 0018), forming the multilayer inner spacer (Figure 16B, references 240, 242 and 260) comprising: depositing the inner layer (Figure 6B, reference 240) on a recessed portion (Figure 5B, reference 236) of the plurality of semiconductor material layers (Figure 6B, reference 206); depositing the middle layer (Figure 7B, reference 242) on the inner layer (Figure 7B, reference 240); and depositing the outer layer (Figure 14B, reference 260)on the middle layer (Figure 14B, reference 242), the outer layer (Figure 16B, reference 260) adjacent a source region and a drain region (Figure 16B, reference 244).
However, Chiang et al does not specifically state the structure is a superlattice structure.
Lee et al disclose the structure is a superlattice structure (column 3, lines 28-33).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Chiang et al with the teachings of Lee et al for the purpose of forming alternating thin semiconductor layers in a structure to produce a super lattice structure that improves uniformity of the semiconductor channel layer thicknesses in GAA devices.
Regarding claim 3, Chiang et al discloses wherein one or more of the inner layer (Figure 16B, reference 240) or the outer layer (Figure 16B, reference 260) has a thickness in a range of from 0.5 nm to 2 nm (paragraphs 0031 and 0050).
Regarding claim 4, Chiang et al discloses wherein one or more of the inner layer (Figure 16B, reference 240) or the outer layer (Figure 16B, reference 260) comprises a high-K dielectric material (paragraph 0031).
Regarding claim 5, Chiang et al discloses wherein the high-K dielectric material has a K-value of greater than or equal to 6 (paragraph 0031).
Regarding claim 6, Chiang et al discloses wherein the high-K dielectric material comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), or nitrogen-rich silicon oxycarbonitride (SiOCN) (paragraph 0031).
Regarding claim 7, Chiang et al discloses wherein the middle layer (Figure 16B, reference 242) has a thickness in a range of from 2 nm to 5 nm (paragraph 0032).
Regarding claim 8, Chiang et al discloses wherein the middle layer (Figure 16B, reference 242) comprises a low-K dielectric material (paragraph 0032).
Regarding claim 9, Chiang et al discloses wherein the low-K dielectric material has a K-value of less than or equal to 4.2 (paragraph 0032).
Regarding claim 10, Chiang et al discloses herein the low-K dielectric material comprises one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectrics (paragraph 0032).
Regarding claim 11, Chiang et al discloses wherein the multilayer inner spacer is substantially free of seams and/or voids (Figure 16B, references 240, 242 and 260).
Regarding claim 12, Chiang et al discloses wherein the electronic device is a gate-all-around (GAA) device (paragraph 0015).
Regarding claim 13, Chiang et al discloses further comprising etching one or more of the outer layer (Figure 16B, reference 260) or the middle layer (Figure 16B, reference 242; paragraphs 0033 and 0047).
Regarding claim 14, Chiang et al discloses a method of manufacturing an electronic device (Figure 16B), the method comprising: forming a multilayer inner spacer (Figure 16B, references 240, 242 and 260) comprising an inner layer (Figure 16B, reference 240), a middle layer (Figure 16B, reference 242), and an outer layer (Figure 16B, reference 260) within a structure formed on a top surface of a substrate (Figure 16B, reference 202), the structure comprising a plurality of semiconductor material layers (Figure 6B, reference 206) and a corresponding plurality of channel layers (Figure 16B, reference 208) alternatingly arranged in a plurality of stacked pairs (Figure 16B, references 206 and 208), the plurality of semiconductor material layers comprising silicon germanium (SiGe) (Figure 16B, reference 206; paragraph 0018) and the corresponding plurality of channel layers comprising silicon (Si) (Figure 16B, reference 208; paragraph 0018), forming the multilayer inner spacer (Figure 16B, references 240, 242 and 260) comprising: depositing the inner layer (Figure 6B, reference 240) on a recessed portion (Figure 5B, reference 236) of the plurality of semiconductor material layers (Figure 6B, reference 206); optionally etching the inner layer; depositing the middle layer (Figure 7B, reference 242) on the inner layer (Figure 7B, reference 240); etching a portion of the middle layer (Figure 8B, reference 242; paragraph 0033); depositing the outer layer (Figure 14B, reference 260) on the middle layer (Figure 14B, reference 242), the outer layer (Figure 16B, reference 260) adjacent a source region and a drain region (Figure 16B, reference 244); and etching the outer layer (paragraph 0047).
However, Chiang et al does not specifically state the structure is a superlattice structure.
Lee et al disclose the structure is a superlattice structure (column 3, lines 28-33).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Chiang et al with the teachings of Lee et al for the purpose of forming alternating thin semiconductor layers in a structure to produce a super lattice structure that improves uniformity of the semiconductor channel layer thicknesses in GAA devices.
Regarding claim 15, Chiang et al discloses performed in situ in an integrated deposition and etch processing system (paragraphs 0035 and 0041).
Regarding claim 17, Chiang et al discloses wherein one or more of the inner layer (Figure 16B, reference 240) or the outer layer (Figure 16B, reference 260) comprises a high-K dielectric material (paragraphs 0031 and 0046).
Regarding claim 18, Chiang et al discloses wherein the middle layer (Figure 16B, reference 242) comprises a low-K dielectric material (paragraph 0032).
Regarding claim 19, Chiang et al discloses wherein the multilayer inner spacer is substantially free of seams and/or voids (Figure 16B, references 240, 242 and 260).
Claim(s) 2 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al (US 2020/0381545 A1) in view of Lee et al (12,040,383 B2), further in view of Lin et al (US 2023/0009745 A1).
Chiang et al in view of Lee et al disclose all of the above claimed subject matter.
However, Chiang et al and Lee et al do not disclose wherein the multilayer inner spacer is formed by a thermal chemical vapor deposition process at a temperature in a range of from 400C to 650C (claims 2 and 16).
Lin et al discloses wherein the multilayer inner spacer is formed by a thermal chemical vapor deposition process at a temperature in a range of from 400C to 650C (paragraph 0020).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Chiang et al and Lee et al, with the teachings of Lin et al for the purpose forming a multilayer inner spacer by a thermal chemical vapor deposition process at a temperature in a range of from 400C to 650C in order to prevent diffusion of the high-k dielectric material from a gate dielectric in semiconductor devices.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pal et al (US 2022/0246742) in view of Chiang et al (US 2020/0381545 A1).
Pal et al discloses a processing tool (Figure 3) comprising: a central transfer station (Figure 3, reference 314) comprising a robot (Figure 3, reference 316) configured to move a substrate (paragraph 0063); a plurality of process stations (Figure 3, reference 308, 310 and 312), each process station (Figure 3, reference 308, 310 and 312) connected to the central transfer station (Figure 3, reference 314; paragraph 0064) and providing a processing region separated from processing regions of adjacent process stations (paragraph 0064), the plurality of process stations comprising a chemical vapor deposition (CVD) chamber and an etch chamber (paragraph 0037); and a controller (Figure 3, reference 357) connected to the central transfer station (Figure 3, reference 314) and the plurality of process stations (Figure 3, reference 308, 310 and 312), the controller (Figure 3, reference 357) configured to activate the robot to move the substrate between process stations (paragraphs 0069-0070), and to control a process cycle for manufacturing a spacer for a gate-all-around (GAA) device (paragraphs 0063-0070) and a superlattice structure (Figure 2E, reference 204).
However, Pal et al does not disclose the spacer is a multilayer inner spacer comprising an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of the substrate, the superlattice structure comprising a plurality of semiconductor material layers and a corresponding plurality of channel layers alternatingly arranged in a plurality of stacked pairs, the plurality of semiconductor material layers comprising silicon germanium (SiGe) and the corresponding plurality of channel layers comprising silicon (Si), the process cycle comprising forming the multilayer inner spacer by a thermal chemical vapor deposition (CVD) process including: depositing the inner layer on a recessed portion of the plurality of semiconductor material layers; depositing the middle layer on the inner layer; and depositing the outer layer on the middle layer, the outer layer adjacent a source region and a drain region.
Chiang et al discloses the spacer is a multilayer inner spacer (Figure 16B, references 240, 242 and 260) comprising an inner layer (Figure 16B, reference 240), a middle layer (Figure 16B, reference 242), and an outer layer (Figure 16B, reference 260) within a structure formed on a top surface of a substrate (Figure 16B, reference 202), the structure comprising a plurality of semiconductor material layers (Figure 16B, reference 206) and a corresponding plurality of channel layers (Figure 16B, reference 208) alternatingly arranged in a plurality of stacked pairs (Figure 16B, references 206 and 208), the plurality of semiconductor material layers comprising silicon germanium (SiGe) (Figure 16B, reference 206; paragraph 0018) and the corresponding plurality of channel layers comprising silicon (Si) (Figure 16B, reference 208; paragraph 0018), forming the multilayer inner spacer (Figure 16B, references 240, 242 and 260) comprising: depositing the inner layer (Figure 6B, reference 240) on a recessed portion (Figure 5B, reference 236) of the plurality of semiconductor material layers (Figure 6B, reference 206); depositing the middle layer (Figure 7B, reference 242) on the inner layer (Figure 7B, reference 240); and depositing the outer layer (Figure 14B, reference 260)on the middle layer (Figure 14B, reference 242), the outer layer (Figure 16B, reference 260) adjacent a source region and a drain region (Figure 16B, reference 244).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Pal et al with the teachings of Chiang et al , for the purpose of forming a multilayer inner spacer, arranged on a superlattice structure that contain a plurality of alternating channel layers and semiconductor material layers, in contact with a source and drain region in order to protect the gate in a GAA structure.
Conclusion
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
December 17, 2025