Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 10/24/2023.
(b) Priority date: 05/26/2023.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1-4, 9, 14, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record “Ali” <US 20180300440 A1>.
(As to claim 1, 9, 14, Ali discloses):1. A method comprising:
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receiving an integrated circuit design comprising a plurality of circuit modules [Fig. 3, 380];
partitioning the integrated circuit design into a plurality of partitions in accordance with the plurality of circuit modules [Fig. 3, 320, 330];
assigning the plurality of partitions of the integrated circuit design to corresponding portions of an emulation system [Fig. 3, buffer (325), HVL (330)];
inserting, by a processor, a plurality of emulation communication circuit structures into the plurality of circuit modules of the integrated circuit design [Fig. 3, 310 (interface unit)],
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the corresponding portions of the emulation system being configured to communicate via one or more emulation interconnects connected to the emulation communication circuit structures [Fig. 1A, 1B; Notice that the Emulator (120), is configured to communicate with various connected circuit structures (130, 180)],
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the emulation communication circuit structures being represented at a representation level selected from a group comprising [Fig. 1A, 1B]:
a packet level [Fig. 8, 840];
a transaction level [0041, “transaction-level interface or to a physical device through a transaction-level interface and a “virtual device” acting as a bridging device”]; and
a protocol level [Fig. 8, “<Protocol>”]; and
emulating operation of the integrated circuit design using the emulation system [Fig. 1A, 120].
(As to claim 2, Ali discloses):2. The method of claim 1, wherein the portions of the emulation system comprise one or more components selected from a group comprising:
a field programmable gate array [0042: In addition to emulators, reconfigurable hardware modeling devices also include FPGA prototyping devices.];
a board comprising a plurality of field programmable gate arrays; and a computer system connected to a plurality of boards of field programmable gate arrays [0047: “FIG. 1B illustrates an example of an emulation circuit board 130. The emulation circuit board 130 includes an array of emulation devices 140. The emulation devices 140 can be programmed to model, for example, combinatorial logic components, sequential circuit components and memories. The emulation devices 140 may be processor-based or FPGA-based.”].
(As to claim 3, Ali discloses):3. The method of claim 2, wherein the emulation interconnects comprise one or more interconnects selected from a group comprising:
a low-voltage differential signaling interconnect [0008: “PCIe” “NVMe”, “SATA/SAS”; Note: LVDS (low-voltage differential signal) is well known in the art to be useful in the serial/parallel protocols, as mentioned above.];
a multi-gigabit transceiver [0056: “wireless transceiver”];
a backplane of an emulation unit [Fig. 1A, 1B]; and an
Ethernet connection [0056: “Ethernet connection”].
(As to claim 4, Ali discloses):4. The method of claim 1, further comprising supplying the plurality of circuit modules separately to an emulation compiler to generate a plurality of compiled circuit modules [Fig. 1A, 1B].
Allowable Subject Matter
The following claims would be allowable if all rejections/objections cited in this office action (if any) are overcome and rewritten to include all of the limitations of the base claim and any intervening claims.The reason for this allowance is: the claimed subject matter could not have been anticipated or obviated using any prior arts.Allowable claims are: 5-8, 10-13 and 15-20.
Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851
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