DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 - 8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LIAW (20210057281).
With regard to claim 1, LIAW discloses an integrated circuit structure (for example, see fig. 9), comprising:
a conductive via (referred to as “V1” by examiner’s annotation shown in fig. 9 below; wherein the via V1, having a conductive material 218j or 230, functioning as a conductive via) above a semiconductor substrate (referred to as “200A” by examiner’s annotation shown in fig. 9 below), the conductive via (V1) comprising a metal-containing material (a conductive material 218j, made of SiGe containing Ge with properties having a metal material and Si is a containing material, functioning as a metal-containing material; or Silicide material 230 inherently including a metal and a containing material is silicon; for example, see paragraph [0080]);
a nanowire (210c) above a fin (referred to as “200B” by examiner’s annotation shown in fig. 9 below) protruding from the semiconductor substrate (200A),
a channel region (the nanowire 210c having a channel region; for example, see paragraph [0097]) of the nanowire (210c) electrically isolated from the fin (200B), wherein the fin (200B) is in contact with the metal-containing material (218j) of the conductive via (V1); or wherein the fin (200B) is indirectly contact with the metal-containing material (230) of the conductive via (V1); and
a gate stack (layers 220c, 212 functioning as a gate stack) over the nanowire (210c).
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With regard to claim 2, LIAW discloses a second conductive via (referred to as “V2” by examiner’s annotation shown in fig. 9 above; wherein the via V2, having a conductive material 225c, functioning as a second conductive via) on the semiconductor substrate (200A), the second conductive via (V2) laterally adjacent to the conductive via (V1).
With regard to claim 3, LIAW discloses a pair of epitaxial source or drain structures (the regions 218i and 218j are the epitaxial source/drain regions, so the epitaxial region 218i can be the epitaxial source region and the epitaxial region 218j also can be the epitaxial source region; for example, see paragraph [0080]. Therefore, the regions 218i and 218j function as a pair of epitaxial source/drain structures; for example, see paragraph [0080]) at first and second ends of the nanowire (210c).
With regard to claim 4, LIAW discloses a pair of conductive contacts (conductive layers 240i and 240j function as a pair of conductive contacts) on the pair of epitaxial source/drain structures (218i, 218j).
With regard to claim 5, LIAW discloses one (240j) of the pair of conductive contacts (240i, 240j) is electrically connected to the conductive via (V1).
With regard to claims 3, 6, LIAW discloses a pair of epitaxial source or drain structures (referred to as “218A” and “218B” by examiner’s annotation shown in fig. 9 below) at first and second ends (bottom and top ends) of the nanowire (210c); wherein the pair of epitaxial source/drain structures (referred to as “218A” and “218B” by examiner’s annotation shown in fig. 9 below) is a pair of non-discrete epitaxial source or drain structures.
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With regard to claim 7, LIAW discloses the pair of epitaxial source/drain structures (218i, 218j) is a pair of discrete epitaxial source/drain structures.
With regard to claim 8, LIAW discloses the gate stack (220c, 212) comprises a high-k gate dielectric layer (212; for example, see paragraph [0055]) and a metal gate electrode (220c; for example, see paragraph [0056]).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9 – 16, 19, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (9978835).
With regard to claim 9, Yang et al. disclose an integrated circuit structure (for example, see fig. 2), comprising:
a nanowire (120) above a fin (an active region 114 functioning as a fin) protruding from a semiconductor substrate (110), a channel region (122) of the nanowire (120) electrically isolated from the fin (114);
a gate stack (layers including a gate electrode 130 and a gate dielectric layer 132 directly contact with the gate electrode 130, functioning as a gate stack) over the nanowire (120);
a pair of epitaxial source or drain structures (the regions 140, 142 are epitaxial source/drain structures; wherein the epitaxial region 140, forming at a first end or bottom side of nanowire 120, can be the epitaxial source region; and the epitaxial region 142, forming at a second end or top side of nanowire 120, can be another epitaxial source region; or the epitaxial region 140, forming at a first end or left side of nanowire 120, can be the epitaxial source region; and the epitaxial region 142, forming at a second end or right side of nanowire 120, can be another epitaxial source region; for example, see column 6, lines 11, 12 and lines 16, 17; for example, see column 6, lines 11, 12 and lines 16, 17. Therefore, the regions 140 and 142 function as a pair of epitaxial source or drain structures) at first and second ends of the nanowire (120); and
a pair of conductive contacts (162, 164) on corresponding ones of the pair of epitaxial source or drain structures (140, 142), one (164) but not both of the pair of conductive contacts (162, 164) comprising a metal-containing material (the contact 164 made of a metal silicide material functioning as a metal-containing material) indirectly contact with the fin (114).
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With regard to claim 10, Yang et al. disclose the pair of epitaxial source or drain structures (the epitaxial region 140, forming at a bottom side of nanowire 120, can be the epitaxial source region; and the epitaxial region 142, forming at a top side of nanowire 120, can be another epitaxial source region; for example, see column 6, lines 11, 12 and lines 16, 17) is a pair of non-discrete epitaxial source or drain structures.
With regard to claim 11, Yang et al. disclose the pair of epitaxial source or drain structures (the regions 140, 142 are epitaxial source/drain structures; wherein the epitaxial region 140, forming at a first end or left side of nanowire 120, can be the epitaxial source region; and the epitaxial region 142, forming at a second end or right side of nanowire 120, can be another epitaxial source region; for example, see column 6, lines 11, 12 and lines 16, 17) is a pair of discrete epitaxial source or drain structures.
With regard to claim 12, Yang et al. disclose the gate stack (layers including a gate electrode 130 and a gate dielectric layer 132 directly contact with the gate electrode 130, functioning as a gate stack) comprises a high-k gate dielectric layer (132; for example, see column 5, lines 56 – 62) and a metal gate electrode (130).
With regard to claim 13, Yang et al. disclose the nanowire (120) is a silicon nanowire. (for example, column 5, lines 50 – 51).
With regard to claim 14, Yang et al. disclose a computing device (a display driver IC 500, fig. 29, acting as a computing device because the display driver IC 500 having the crucial interface between a device’s processor and the screen, converting high-speed digital data into precise voltage/current signals to control individual pixels, manage brightness color.), comprising:
a board (a power supply circuit 504 inherently having a board or functioning as a board; or a main processing unit MPU 522 inherently having a circuit board); and
a component (a driver block 506 functioning as a component) coupled to the board (504), the component (506) including an integrated circuit structure (100B; for example, see column 23, lines 15 – 17), comprising:
a conductive via (referred to as “V3” by examiner’s annotation shown in fig. 2 below; wherein the via V3, having a conductive material 164, functioning as a conductive via) above a semiconductor substrate (110), the conductive via (V3) comprising a metal-containing material (the contact 164 made of a metal silicide material functioning as a metal-containing material);
a nanowire (120) above a fin (an active region 114 functioning as a fin) protruding from the semiconductor substrate (110), a channel region (122) of the nanowire (120) electrically isolated from the fin (114), wherein the fin (114) is indirectly contact with the metal-containing material (164) of the conductive via (V3);
a gate stack (layers including a gate electrode 130 and a gate dielectric layer 132 directly contact with the gate electrode 130, functioning as a gate stack) over the nanowire (120).
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With regard to claim 15, Yang et al. disclose a memory (508, fig. 29) coupled to the board (504, fig. 29).
With regard to claim 16, Yang et al. disclose a communication chip (the processing unit 522 inherently including a communication chip) coupled to the board (504).
With regard to claim 19, Yang et al. disclose the component (the driver block 506) functioning as a packaged integrated circuit die.
With regard to claim 20, Yang et al. disclose the component (the driver block 506) inherently functioning as a communications chip.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (9978835) in view of Yamazaki et al. (12237389).
With regard to claim 17, Yang et al. do not clearly disclose a battery coupled to the board.
However, Yamazaki et al. disclose a battery (6011) coupled to the board (6010). (for example, see fig. 22B).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Yang et al.’s device to have a battery coupled to the board as taught by Yamazaki et al. in order to secure the electrical power efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (9978835) in view of Yamazaki et al. (12237389).
With regard to claim 18, Yang et al. do not clearly disclose a camera coupled to the board.
However, Yamazaki et al. disclose a camera (6507) coupled to the board (6517). (for example, see figs. 23A, 23B).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Yang et al.’s device to have a camera coupled to the board as taught by Yamazaki et al. in order to enhance a high efficiency of the display and enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Response to Arguments
Applicant’s arguments filed 04/15/26 have been fully considered but they are not persuasive.
It is argued, at pages of the remarks, that “Liaw does not disclose an integrated circuit structure including a conductive via above a semiconductor substrate, the conductive via comprising a metal-containing material, a fin protruding from the semiconductor substrate, where the fin is in contact with the metal-containing material of the conductive via”. However, fig. 9 below of Liaw does show a conductive via (referred to as “V1” by examiner’s annotation shown in fig. 9 below; wherein the via V1, having a conductive material 218j or 230, functioning as a conductive via) above a semiconductor substrate (referred to as “200A” by examiner’s annotation shown in fig. 9 below), the conductive via (V1) comprising a metal-containing material (a conductive material 218j, made of SiGe containing Ge with properties having a metal material and Si is a containing material, functioning as a metal-containing material; or Silicide material 230 inherently including a metal and a containing material is silicon; for example, see paragraph [0080]); wherein the fin (200B) is contact with the metal-containing material (218j) of the conductive via (V1) or wherein the fin (200B) is indirectly contact with the metal-containing material (230) of the conductive via (V1);
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Conclusion
8. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812
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