DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (20150287907).
Regarding Claim 1, in Figs. 4B and 9B and paragraphs 0078, 0079, 0114, 0115, 0138, 0139, 0141, 0157, 0182, 0185, 0186 and 0203, Park et al. discloses a semiconductor device, comprising: a gate electrode CG on a semiconductor substrate 100; a gate dielectric pattern 101c between the gate electrode and the semiconductor substrate; a first semiconductor (namely doped silicon as disclosed in the ends of paragraphs 0078 and 0079) pattern 110/112 on the semiconductor substrate adjacent to a first (left) side of the gate electrode CG; and a second semiconductor pattern 110/112 (left side) on the semiconductor substrate adjacent to a second (right) side of the gate electrode, wherein the first semiconductor pattern 110/112 includes: a first via part 110 in contact with the semiconductor substrate 100; and a first plate part 112 on the first via part, wherein the second semiconductor pattern 110/112 (right side) includes: a second via part 110 in contact with the semiconductor substrate 100; and
a second plate part 112 on the second via part, wherein each of the first and second plate parts 112 extends lengthwise in a direction parallel to a top surface of the semiconductor substrate 100.
Regarding Claim 2, in further comprising: a first contact plug 180 (Fig. 9B) connected to the first plate part 112 (left portion); and a second contact plug 180 connected to the second plate part 112 (right side) wherein the first plate part 112 includes a first contact region (middle portion) that overlaps the first contact plug 180,
wherein the second plate part 112 includes a second contact region (middle portion) that overlaps the second contact plug 180, wherein the first contact region has an impurity concentration greater than an impurity concentration of the first via part, and
wherein the second contact region has an impurity concentration greater than an
impurity concentration of the second via part (see paragraphs 0079, 0080, 0115 and 0116)
Regarding Claim 3, a source region 102 in the semiconductor substrate, the source region overlapping the first via part 110; and a drain region 102 in the semiconductor substrate, the drain region overlapping the second via part 110,
wherein the impurity concentration of the first contact region is greater than an
impurity concentration of the source region, and wherein the impurity of the second contact region is greater than an impurity concentration of the drain region (see paragraphs 0078, 0079, 0113, 0114, 0139)
Regarding Claim 4, the first via part (the right end portion of 110 on the left) is closer to the gate electrode CG than the second via part (the right end of element 110 on the right side).
Regarding Claim 5, a lower interlayer dielectric layer 182 (see Fig. 20) on the semiconductor substrate 100, the lower interlayer dielectric layer 182 covering the gate electrode CG and the first and second plate parts 112, wherein the first and second contact plugs 180 penetrate the lower interlayer dielectric layer 182.
Regarding Claim 6, top surfaces of the first and second semiconductor patterns 110/112 are at a vertical level lower than a vertical level of a top surface of the gate electrode CG (one can flip the device).
Regarding Claim 7, top surfaces of the first and second semiconductor patterns 110/112 are at a vertical level higher than a vertical level of a top surface of the gate electrode CG.
Regarding Claim 8, the first and second semiconductor patterns 110/112 are symmetrical to each other about the gate electrode CG
Regarding Claim 9, the first and second semiconductor patterns 110/112 are asymmetrical to each other about the gate electrode CG (once can arrive at the asymmetrical relationship if one takes different portions of element 110/112 when comparing)
Regarding Claim 10, the gate electrode CG extends (lateral/horizontal/x-direction) in a first direction parallel to the top surface of the substrate 110, the first plate part 112 extends lengthwise in the first direction, and the second plate part 112 extends lengthwise in a second direction that intersects the first direction (once can arrive at this since the plate part 112 has a two dimensional/box configuration).
Regarding Claim 17, in Figs 3, 4A and 12 and in paragraphs 0067, 0164 and 0176, Park et al. discloses a semiconductor device, comprising: a peripheral circuit structure (see paragraph 0164) that includes peripheral circuits integrated on a semiconductor substrate 100; and a cell array structure (see paragraph 0164) on the peripheral circuit structure and including memory cells that are three-dimensionally arranged (see Fig. 4A, stacked) on a semiconductor layer, wherein the peripheral circuit structure includes: a gate electrode CG on the semiconductor substrate 100; a gate dielectric pattern 101C between the gate electrode and the semiconductor substrate;
a source region 102 and a drain region 10 in the semiconductor substrate 100, and
adjacent to a corresponding one of opposite sides of the gate electrode, respectively;
a plurality of semiconductor patterns 110/112 correspondingly coupled to the
source region and the drain region, each of the semiconductor patterns (see paragraphs 0078 and 0079) including a via part 110 that penetrates a dielectric layer 106 on the semiconductor substrate and a plate part 112 connected to the via part on the dielectric layer; and a plurality of contact plugs 180 correspondingly coupled to the plurality of
semiconductor patterns, each of the contact plugs being in contact with a portion of the
plate part 112, wherein the plate part 112 extends lengthwise in a direction parallel to a top surface of the semiconductor substrate 100.
Regarding Claim 18, when viewed in a plan, the contact plugs 180 are correspondingly spaced apart from the via parts 110.
Regarding Claim 19, wherein top surfaces of the plate parts 112 are at a vertical level lower than a vertical level of a top surface of the gate electrode CG (the device of Park could be in flipped orientation).
Regarding Claim 20, in Fig. 4A and paragraphs 0090, 0128 and 0197, the cell array structure includes: a stack structure that includes conductive patterns (MTJ/180/112/110) and interlayer dielectric layers106/160 that are vertically and alternately stacked; a plurality of vertical structures that penetrate the stack structure; and a plurality of bit lines BL that run across the stack structure and are connected to the vertical structures, wherein lengths in a first direction of the conductive patterns decrease (MTJ/180/112/110) as the conductive patterns increase in distance from a top surface of the semiconductor substrate (see Fig. 9B).
Claims 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Togo (20220109054)
Regarding Claim 11, in Figs. 32A-32G and paragraphs 0195,0197, 0201, and 0202, Togo discloses a semiconductor device, comprising: a device isolation layer 20 that defines an active region (under gate electrode 52) on a semiconductor substrate;
a gate electrode 52 disposed on the active region; a gate dielectric pattern 50 between the gate electrode and the semiconductor substrate; a semiconductor pattern (doped polysilicon see paragraphs 0195 and 0197) (133S/134S on a first (left) side of the gate electrode, wherein the semiconductor pattern includes a via part 133S (see Fig. 32B) in contact with the semiconductor substrate and a plate part 134S (see Fig. 32D) (134S is a box/rectangular two dimensional shaped which can be called a plate) on the via part; and a contact plug 98S in contact with a portion of the plate part 1334S and spaced apart from the via part 133S when viewed in a plan (please note that 98S could be called a plug since it is a plug/pillar shaped and it can be both a plug/pillar and via as it is called by Togo)
Regarding Claim 12, the (very bottom portion of contact plug) 98S is closer
to the gate electrode 52 than the (very bottom left portion of) via part 133S.
Regarding Claim 13, the (middle portion of) via part 133S is closer to the gate electrode 52 than the (very top portion of) contact plug 98S.
Regarding Claim 14, a dielectric pattern 62 that covers the gate electrode 52,
wherein the dielectric pattern extends along the first side of the gate electrode and onto a top surface of the semiconductor substrate, and wherein the via part 133S penetrates the dielectric pattern 62 (see Fig. 32G).
Regarding Claim 15, the plate part 134S is on the dielectric pattern 62.
Regarding Claim 16, a first lower interlayer dielectric layer 70 (lower portion of element 70 on the very left or very right side) that covers a portion of the dielectric pattern 62 (see paragraph 0110); and a second lower interlayer dielectric layer 70 (very top portion of element 70 in the middle) on the first lower interlayer dielectric layer,
wherein the via part 133S further penetrates the first lower interlayer dielectric layer 70,
wherein the plate part 134S is on the first lower interlayer dielectric layer, and wherein a top surface of the first lower interlayer dielectric layer is at a vertical level higher than a vertical level of a top surface of the gate electrode 54.
Pertinent Prior Art References that are NOT relied Upon
Nishikawa (20160351709) (doped epitaxial contact structure to source/drain regions)
Iwata (20190296012) (doped epitaxial contact structure to source/drain regions)
Choi (20190371808) (doped semiconductor via structure)
Seo (20220208783) (increased current path between source and drain to increased junction breakdown voltage) (see paragraph 0082)
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 2/16/2026