DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5, 8-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIAO (US 2021/0335599).
LIAO discloses a EUV photomask and related methods using the mask. LIAO illustrates an EUV mask structure in Figure 2. (Para, 0022; Fig.2). LIAO discloses the EUV mask 108 may include a substrate 202 having a backside coating layer 203, a multi-layer structure 204, a capping layer 206, and one or more absorbers 208 having an anti-reflective coating (ARC) layer 210. (Para, 0022; Fig.2). These disclosures and the illustrations of Figure 2 teach and/or suggest the limitation of claim 1, ‘An extreme ultraviolet (EUV) reflective mask, comprising: a mask substrate, a reflection layer on the mask substrate, and an absorption layer on the reflection layer…’ LIAO discloses the substrate 202 includes a low thermal expansion material (LTEM) substrate (e.g., such as TiO2 doped SiO2), and the backside coating layer 203 includes a chromium nitride (CrxNy) layer. (Para, 0022).
LIAO discloses the multi-layer structure 204 may include molybdenum-silicon (Mo—Si) multi-layers deposited on top of the substrate 202. (Para, 0022). LIAO discloses the capping layer 206 includes a ruthenium (Ru) capping layer or the capping layer 206 may include a Si capping layer. (Para, 0022; Fig.2). LIAO explains the capping layer 206 may help to protect the multi-layer structure 204 (e.g., during fabrication of the mask 108) and may also serve as an etch-stop layer for a subsequent absorber layer etch process. (Para, 0022). LIAO discloses the absorbers 208 may include for example, a TaBO layer, a TaBN layer, a TaBO/TaBN layer, a TaxNy layer, a TaxByONu layer, or a combination thereof, and are configured to absorb EUV light (e.g., with a wavelength of about 13.5 nm). (Para, 0022; Fig.2). LIAO discloses other materials may be used for the absorbers 208, such as Al, Cr, Ta, and W, among others. (Para, 0022; Fig.2). In some examples, the ARC layer 210 includes at least one of a TaxByOzNu layer, a HfxOy layer, or a SixOyNz layer. (Para, 0022; Fig.2).’ LIAO also discloses the mask 108 may be fabricated to include different structure types such as, for example, a binary intensity mask (BIM) or a phase-shifting mask (PSM). (Para, 0024; Fig.2). LIAO explains the mask 108 may include a PSM which utilizes interference produced by phase differences of light passing therethrough. (Para, 0024; Fig.2). LIAO discloses examples of PSMs include an alternating PSM (AltPSM), an attenuated PSM (AttPSM), and a chromeless PSM (cPSM). (Para, 0024; Fig.2). These disclosures and the illustrations of Figure 2 teach and/or suggest the limitations of claim 10.
LIAO discloses the mask 108 includes a patterned image that may be used to transfer circuit and/or device patterns onto a semiconductor wafer (e.g., the semiconductor substrate 116) by the lithography system 100. (Para, 0025). LIAO explains main pattern area may include regions where the absorber layer has been patterned to define various features (e.g., as part of a device and/or circuit) for transfer to a semiconductor wafer as part of a photolithography process. (Para, 0030). LIAO discloses the one or more openings disclosed herein may be disposed a sufficient distance away from the main pattern area so the features defined by the main pattern area can be transferred to the semiconductor wafer (e.g., by an EUV lithography process) with high-fidelity with substantially no impact from the one or more openings.(Para, 0030). LIAO illustrates this further with the mask illustrated in Figures 4A/4B. (Para, 0032). These disclosures and illustrations teach and/or suggest the limitation of claim 1, ‘ An extreme ultraviolet (EUV) reflective mask, comprising: …wherein the absorption layer comprises a main pattern and non-diffraction patterns near the main pattern’
LIAO discloses exemplary mask 402 includes one or more openings formed within an opening area. (Para, 0032; Fig.4B). LIAO discloses the mask 402 may be similar to the mask 108, and the mask 402 may be used in a lithography system such as the lithography system 100. (Para, 0032; Fig.1-2, 4A/4B). LIAO discloses mask 402 may include a substrate 410, a multi-layer structure 412, a capping layer 414, and an absorber layer 416, which may be substantially the same as the substrate 202, the multi-layer structure 204, the capping layer 206, and the absorber layer 208. (Para, 0032; Fig.4B). LIAO discloses the mask 402 may also include a backside coating layer (e.g., such as the backside coating layer 203) and an ARC layer (e.g., such as the ARC layer 210). (Para, 0032; Fig.4B).
LIAO discloses the mask 402 includes a first main pattern area 404 and a second main pattern area 406, which may be similar to the main pattern areas 304, 306. (Para, 0032; Fig.4B). LIAO explains the main patterns areas 404, 406 may include regions where the absorber layer 416 has been patterned, for example, to define various features (e.g., as part of a device and/or circuit) for transfer to a semiconductor wafer as part of a photolithography process using the mask 402. (Para, 0032; Fig.4B). LIAO discloses mask 402 includes an opening area 408 between the main pattern areas 404, 406 and away from the main pattern areas 404, 406. (Para, 0033; Fig.4B). LIAO explains in contrast to the main pattern areas 404, 406, the opening area 408 may not necessarily define features which form part of a semiconductor device and/or circuit. (Para, 0034; Fig.4B). LIAO also discloses an opening area need not necessarily be disposed between two main pattern areas and a plurality of opening areas (each having at least one opening) may be disposed within different portions of the mask, as long as each opening area is spaced a sufficient distance away from an adjacent main pattern area, as described further herein. (Para, 0033; Fig.4B). These disclosures and illustrations teach and/or suggest the limitation of claim 1, ‘ An extreme ultraviolet (EUV) reflective mask comprising: … and the main pattern is isolated from the non-diffraction patterns.’ These disclosures also teach and/or suggest the limitation of claims 2, 8 and 20.
LIAO discloses the opening area 408, as well as any other opening areas on the mask 402, includes at least one opening within the absorber layer 416 of the mask 402 that exposes the underlying capping layer 416. (Para, 0033). LIAO discloses opening area 408 is spaced a distance ‘D1’ from the main pattern area 404 and a distance ‘D2’ from the main pattern area 406. (Para, 0033; Fig.4B). LIAO explains distance ‘D1’ may be the same as or different from the distance ‘D2’. LIAO discloses some examples where each of the distances ‘D1’ and ‘D2’ may be less than or equal to about 5 microns. (Para, 0033; Fig.4B). LIAO discloses the distances ‘D1’ and ‘D2’ between the opening area 408 and respective main pattern areas 404, 406, the main pattern areas 404, 406 will not be affected by openings formed within the opening area 408. (Para, 0033; Fig.4B). LIAO explains the distances ‘D1’ and ‘D2’ between the opening area 408 and respective main pattern areas 404, 406 ensure the features defined by the main pattern areas 404, 406 can be transferred to a semiconductor wafer (e.g., by an EUV lithography process) using the mask 402 with high-fidelity and with substantially no impact from openings formed within the opening area 408. (Para, 0033; Fig.4B). These disclosures and illustrations of Figure 6 teach and/or suggest the limitation of claim 1, ‘An extreme ultraviolet (EUV) reflective mask comprising: …a pitch between the non-diffraction patterns is less than a diffraction limit…’
LIAO illustrated in Figure 5-11, exemplary embodiments of various shapes, mask layouts, and sizes of openings that may be formed within the opening area (e.g., such as the opening area 408). (Para, 0037; Fig.5-11). LIAO illustrates in Figure 6, a top view of a mask 602, which may be similar to the mask 402, with a different layout design for openings within the opening area 408. (Para, 0039; Fig.6). LIAO discloses the opening area 408 is disposed between the main pattern areas 404, 406 and spaced away from the main pattern areas 404, 406 by a distance ‘D1’ and ‘D2’, where each of the distances ‘D1’ and ‘D2’ may be less than or equal to about 5 microns. (Para, 0038: Fig.6). LIAO discloses, mask 602 includes a plurality of oval/round openings 604 disposed within the opening area 408. (Para, 0038; Fig.6). LIAO explains the plurality of oval/round openings 604 may be arranged in an array pattern. (Para, 0038; Fig.6). LIAO discloses each of the plurality of oval/round openings 604 may have a width ‘W’ that is less than or equal to about 20 nm, and a spacing ‘S’ between adjacent openings may be less than or equal to about 1 micron. (Para, 0038; Fig.6). These disclosures and the illustrations of Figure 6 teach and/or suggest the limitation of claim 1, ‘ An extreme ultraviolet (EUV) reflective mask comprising: … the non-diffraction patterns form a honeycomb shape…’ and the limitation of claims 5, 9 and 17.
LIAO also discloses a lithography system in which the EUV mask is used to form a pattern for fabricating a semiconductor device. (Para, 0016; Fig.1). LIAO discloses the lithography system 100 may also be generically referred to as a scanner that is operable to perform lithographic processes including exposure with a respective radiation source and in a particular exposure mode. (Para, 0016; Fig.1). LIAO discloses the lithography system 100 includes an extreme ultraviolet (EUV) lithography system designed to expose a resist layer by EUV light. (Para, 0016; Fig.1). LIAO discloses the lithography system 100 of FIG. 1 includes a plurality of subsystems such as a radiation source 102, an illuminator 104, a mask stage 106 configured to receive a mask 108, projection optics 110, and a substrate stage 118 configured to receive a semiconductor substrate 116. (Para, 0016; Fig.1). LIAO discloses the radiation source 102 may be used to generate the EUV light. (Para, 0017; Fig.1). LIAO also discloses light from the radiation source 102 is directed toward the illuminator 104. (Para, 0018; Fig.1). LIAO discloses the illuminator 104 may be configured to shape the EUV light passing therethrough in accordance with a particular pupil shape, and including for example, a dipole shape, a quadrupole shape, an annular shape, a single beam shape, a multiple beam shape, and/or a combination thereof. (Para, 0018; Fig.1). These disclosures teach and/or suggest the limitation of claim 3 and 19.
LIAO also discloses a method of using the EUV mask disclosed. (Para, 0045; Fig.12). LIAO discloses the method 1200 begins at block 1202 where an EUV mask is fabricated. (Para, 0045; Fig.12). LIAO discloses the fabricated EUV mask may include any of the masks 108, 402, 502, 602, 702, 802, 902, 1002, or 1102, discussed above. (Para, 0045). LIAO discloses next the method 1200 proceeds to block 1204 where a photolithography process is performed using the patterned EUV mask. (Para, 0046; Fig.12). LIAO discloses the patterned EUV mask may be used to transfer circuit and/or device patterns onto a semiconductor wafer using an EUV lithography system (e.g. such as the system 100). (Para, 0046; Fig.12). LIAO discloses a flow chart with a more detailed method 1300 for manufacturing a semiconductor device and/or IC using an EUV mask. (Para, 0047; Fig.13, 14A-14E). These disclosures and the disclosures of LIAO as discussed above teach and/or suggest the limitations of claim 11, ‘A method of fabricating a semiconductor device, comprising: …wherein the EUV reflective mask comprises a main pattern and non-diffraction patterns, the non-diffraction patterns form a honeycomb shape, a pitch between the non-diffraction patterns is less than a diffraction limit, and the hole is printed from the main pattern.’ These disclosures and the disclosures of LIAO as discussed above teach and/or suggest the limitation of claims 12 and 15. These disclosures and illustrations also teach and/or suggest the limitations of claim 16, ‘ A method of fabricating a semiconductor device wherein the EUV reflective mask comprises an isolated pattern and non-diffraction patterns near the isolated pattern, a pitch between adjacent ones of the non-diffraction patterns is less than a diffraction limit, and the hole is printed from the isolated pattern.’
LIAO discloses the method 1300 begins at block 1302 where a substrate is provided. (Para, 0049; Fig.13, 14A-14E). LIAO discloses the substrate 1402 may include a semiconductor substrate such as silicon or alternatively or additionally include other materials such as germanium, silicon carbide (SiC), silicon germanium (SiGe), diamond, compound semiconductors, alloy semiconductors, and the substrate 1402 may optionally include one or more epitaxial layers (epi-layers), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or have other suitable enhancement features. (Para, 0049; Fig.13, 14A-14E). LIAO discloses the substrate 1402 may also include conductive or insulating layers formed on the substrate 1402, and the substrate 1402 may include various doping configurations depending on design requirements as is known in the art. (Para, 0049; Fig.13, 14A-14E). These disclosures and illustrations teach and/or suggest the limitation of claim 16, ‘A method of fabricating a semiconductor device, comprising: forming a front-end-of-line (FEOL) layer on a substrate, the FEOL layer comprising a plurality of transistors on the substrate; forming an interlayer insulating layer on the FEOL layer…’
LIAO discloses the substrate 1402 includes an underlayer (or material layer) 1404 to be processed, such as to be patterned or to be implanted. (Para, 0050). LIAO discloses the underlayer 1404 may include a hard mask layer to be patterned or may include an epitaxial semiconductor layer to be ion implanted. (Para, 0050). LIAO discloses in some embodiments, the substrate 1402 may not include an underlayer and an underlayer (e.g., 1404) is instead optionally formed over the substrate 1402. (Para, 0050). LIAO explains the underlayer 1404 may include a hard mask layer including material(s) such as silicon oxide, silicon nitride (SiN), silicon oxynitride, titanium nitride, or other suitable material or composition or may include an anti-reflection coating (ARC) layer such as a nitrogen-free anti-reflection coating (NFARC) layer including material(s) such as silicon oxide, silicon oxygen carbide, or plasma enhanced chemical vapor deposited silicon oxide. (Para, 0050). LIAO discloses the underlayer 1404 may include a high-k dielectric layer, a gate layer, a hard mask layer, an interfacial layer, a capping layer, a diffusion/barrier layer, a dielectric layer, a conductive layer, other suitable layers, and/or combinations thereof. (Para, 0050). LIAO discloses the method 1300 proceeds to block 1304 where a resist layer (an EUV resist layer, in some examples) 1406 is formed over the substrate 1402, or over the optional underlayer 1404 (Para, 0051; Fig.13, 14A). These disclosures and illustrations teach and/or suggest the limitations of claim 11, ‘A method of fabricating a semiconductor device, comprising: forming an etch target layer, a mask layer, and a photoresist layer sequentially stacked on a substrate…’ and the limitations of claim 16, ‘ A method of fabricating a semiconductor device, comprising: …forming a mask layer and a photoresist layer on the interlayer insulating layer…’
LIAO discloses the method 1300 proceeds to block 1306 where a pattern is exposed onto the resist-coated substrate. (Para, 0052; Fig.13, 14A). LIAO discloses the resist layer 1406 (FIG. 14A) has been exposed (e.g., by a lithographic imaging system) through an intervening mask. In at least some embodiments, the resist layer 1406 is exposed by EUV radiation (e.g., 13.5 nm) using an EUV system (e.g., such as the system 100) and an EUV mask such as any of the masks 108, 402, 502, 602, 702, 802, 902, 1002, or 1102, discussed above. (Para, 0052; Fig.13, 14A-14B). These disclosures and illustrations teach and/or suggest the limitations of claim 11, ‘ A method of fabricating a semiconductor device, comprising: … performing a printing process using an extreme ultraviolet (EUV) reflective mask on the photoresist layer to form a photoresist pattern including a hole…’ and the limitation of claim 16, ‘ A method of fabricating a semiconductor device, comprising: …performing a printing process using an extreme ultraviolet (EUV) reflective mask on the photoresist layer to form a photoresist pattern including a hole…’
LIAO discloses after the exposure of block 1306, a baking process may be performed prior to performing a resist development process, a post-bake process may be performed to stabilize and harden the developed resist layer. (Para, 0053; Fig.13, 14A-14B). LIAO discloses d as a result of the exposure process of block 1306, a latent pattern is formed in the resist layer 1406. By way of example, the latent pattern refers to the exposed pattern on the resist layer 1406, which will subsequently become a physical resist pattern, after a developing process. (Para, 0054; Fig.13,14A-14B). LIAO discloses the method 1300 proceeds to block 1308 where a development process is performed to form a patterned resist layer. (Para, 0054; Fig.13, 14B-14C).
LIAO discloses the method 1300 proceeds to block 1310, where a fabrication process is performed to the substrate through openings of the patterned resist layer. (Para, 0055; Fig.13, 14A-14E). LIAO discloses a fabrication process may be performed to the semiconductor device 1400 using the patterned resist layer 1406′ as a mask, such that the fabrication process is applied to the portions of the semiconductor device 1400 within the openings of the patterned resist layer 1406′ (e.g., the exposed regions of the underlayer 1404), while other portions covered by the patterned resist layer 1406′ are protected from the fabrication process. (Para, 0055; Fig.13, 14A-14E). LIAO discloses the fabrication process of block 1310 may include an etching process applied to the underlayer 1404 using the patterned resist layer 1406′ as an etch mask, thereby transferring the pattern from the patterned resist layer 1406′ to the underlayer 1404. (Para, 0055; Fig.13, 14A-14E). LIAO discloses the underlayer 1404 may include a hard mask layer and so the pattern of the patterned resist layer 1406′ may first be transferred to the underlayer 1404 (e.g., the hard mask layer 1404), forming a patterned hard mask layer 1404′ (FIG. 14D), then to other layers of the substrate 1402. (Para, 0055; Fig.13, 14A-14E). These disclosures and illustrations teach and/or suggest the limitations of claim 11, ‘ A method of fabricating a semiconductor device, comprising: …and patterning the mask layer and the etch target layer using the photoresist pattern as an etch mask…’ and the limitation of claim 16, ‘ A method of fabricating a semiconductor device, comprising: … patterning the mask layer and the interlayer insulating layer using the photoresist pattern as an etch mask…’.
LIAO discloses the method 1300 may include other steps before, during or after the steps described above. (Para, 0057). LIAO discloses in some embodiments, the method 1300 includes other steps to form a plurality of gate electrodes, gate spacers, doped source/drain regions, contacts for gate/source/drain features, etc. (Para, 0057). LIAO also discloses in some embodiments, subsequent processing may form various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, configured to connect the various features to form a functional circuit that may include one or more devices (e.g., one or more FinFET devices). (Para, 0057). LIAO explains that in furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. (Para, 0057). LIAO discloses the various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. (Para, 0057). LIAO discloses in one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. (Para, 0057). These disclosures teach and/or suggest the limitation of claims 13-14. Moreover these disclosures and the disclosures of LIAO as discussed above teach and/or suggest the limitations of claim 16, ‘A method of fabricating a semiconductor device, comprising: … and forming a via pattern or a contact pattern by filling the hole, which is in the interlayer insulating layer, with a metallic material…’ and the limitation of claim 18.
While the recitations of claims 1-3, 5, 8-20 are not exactly and/or identically disclosed
by LIAO one of ordinary skill in the art would have a reasonable expectation to successfully fabricate a semiconductor device using the EUV mask disclosed by LIAO so a semiconductor device is fabricated without any defects that are commonly formed during the lithography process.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIAO as applied to claims 1-3, 5, 8-20 in paragraph 4 above, and further in view of Swanson (US 2020/0019052).
The disclosures and illustrations of LIAO as discussed in paragraph 4 above fail to teach and/or suggest the limitation of claim 5, ‘The EUV reflective mask of claim 3, wherein an outer radius or sigma outer of the annular illumination ranges from 0.7 to 0.9.’ However, the disclosures of LIAO further in view of the disclosures of Swanson provide such teachings.
Swanson is directed to a method of optimizing parameters of a mask and mask constraints data, which includes information on manufacturability limitations that are to be observed for the mask, for example, limitations on minimum widths that could be provided for openings/transparent regions to be defined by the mask. (Abstract). Swanson discloses with respect to parameters data, it is to be noted that an array of variable, user-controlled parameters (referred to herein as “parameters” or “variables”) can influence a lithographic outcome (i.e. the resulting configuration of a wafer layer or plurality of wafer layers after completion of a lithographic process, either in practice or by way of prediction). (Para, 0032). Swanson discloses lithography parameters are well known, and include, by way of example only: mask parameters, such as mask bias and feature transmittance; lithography process parameters, such as post exposure bake time, photoresist development time, hotplate duration, transition duration, chill-plate duration; and lithography tool parameters such as numerical aperture (NA), light source parameters such the outer sigma σout of annular illumination, to name only a few. (Para, 0032). From these disclosures of Swanson, one of ordinary skill in the art would reasonably understand that parameters of a lithography process such as the outer sigma of annular illumination, is a variable to be optimized to achieve a certain result. Therefore, the disclosures of LIAO further in view of these disclosures of Swanson contemplates the limitation of claim 5.
It would have been obvious to one of ordinary skill in the art at the time of filing of the present application by Applicant to modify the disclosures of LIAO further in view of these disclosures of Swanson, because both LIAO and Swanson are directed to improving lithography outcomes and Swanson discloses that many parameters related to the lithography process can be optimized and/or corrected to achieve a desired result such as a defect free pattern.
Allowable Subject Matter
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The disclosures of LIAO and Swanson as discussed above fail to teach and/or suggest the limitation of claim 6, ‘ The EUV reflective mask of claim 1, wherein an intensity of EUV reflection light by the non-diffraction patterns has a flat profile.’ The prior art fails to provide other relevant disclosures which cure the deficiency of LIAO and/or Swanson to teach and/or suggest this limitation of claim 6. Claim 7 depends directly from claim 6. Therefore, claims 6 and 7 include allowable subject matter.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
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